- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic to the Top
- Bookmark
- Subscribe
- Printer Friendly Page
Synthesis results in incorrect netlist without KEEP_HIERA RCHY on.
- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content
04-25-2012 10:30 PM
Hi
I have a very simple piece of Verilog code (see below) that I'm struggling to synthesise correctly using XST (ISE 13.4). Behavioural simulation is correct; however, post-translation simulation is not, neither is generated net-list. If I turn KEEP_HIERARCHY option on during synthesis, then the synthesised netlist is correct and post-translation simulation matches behavioral.
Am I doing something wrong with Verilog?
I have 2 modules. One module is a processing element (PE):
module PE( input L, input C, input R, input AL, input AC, input AR, input BL, input BC, input BR, output [0:0] D_o ); wire [3:0] sum; // Compute how many neighbors are HIGH assign sum = (L + R + AL + AC + AR + BL + BC + BR ); // If 3 are HIGH or 2 are HIGH and Center is HIGH output 1 assign D_o = (sum == 4'd3) || ((sum == 4'd2) && C); endmodule
And another module instantiates 4 of these PEs to process a stream of incoming data (4 bits at a time).
As I need 3x3 neighbourhood, I use a shift register to store 3 of the last data elements. The outputs of the register are connected to the inputs of the instantiated PEs:
module PEarray (
input CLK,
input CE,
input [3:0] Darray_i,
output Darray_o0,
output Darray_o1,
output Darray_o2,
output Darray_o3
);
reg [3:0] left, centre, right; // store previous, current and future data
// Instantiate 4 processing elements
// Each processes a 3x3 neighbourhood: Above left (AC), Above Centre (AC), Above Right (AR)
// Left, Centre, Right
// Below Left(BL), Below Centre (BC), Below right (BR)
PE element0(
.L(left[0]),
.C(centre[0]),
.R(right[0]),
.AL(left[1]),
.AC(centre[1]),
.AR(right[1]),
.BL(0), // Boundary condition: out of bounds = 0
.BC(0),
.BR(0),
.D_o(Darray_o0) );
PE element1(
.L(left[1]),
.C(centre[1]),
.R(right[1]),
.AL(left[2]),
.AC(centre[2]),
.AR(right[2]),
.BL(left[0]),
.BC(centre[0]),
.BR(right[0]),
.D_o(Darray_o1) );
PE element2(
.L(left[2]),
.C(centre[2]),
.R(right[2]),
.AL(left[3]),
.AC(centre[3]),
.AR(right[3]),
.BL(left[1]),
.BC(centre[1]),
.BR(right[1]),
.D_o(Darray_o2) );
PE element3(
.L(left[3]),
.C(centre[3]),
.R(right[3]),
.AL(0), // Boundary condition: out of bounds = 0
.AC(0),
.AR(0),
.BL(left[2]),
.BC(centre[2]),
.BR(right[2]),
.D_o(Darray_o3) );
// One piece of data is fed every clock cycle
// Shift register to store left, centre and right required to process 3x3 neighbourhood
always @(posedge CLK)
begin
right <= Darray_i;
centre <= right;
left <= centre;
end
endmodule
Thanks for help in advance.
Andrew
Re: Synthesis results in incorrect netlist without KEEP_HIERA RCHY on.
- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content
04-26-2012 05:37 PM
I tried rewriting the PE module as a function:
function [3:0] PEf; input L,C,R,AL,AC,AR,BL,BC,BR; begin : PEfunc reg [3:0] sum; sum = L + R + AL + AC + AR + BL + BC + BR; PEf = (sum == 4'd3) || ((sum == 4'd2) && C); end endfunction
And using it in the following way:
assign Darray_o1 = PEf( left[1], centre[1], right[1], left[2], centre[2], right[2], left[0], centre[0], right[0]);
And now the synthesis is correct and so as post-translation simulation.
I really don't understand why it doesn't work as a module... Any hints?











