Hi all,
I try to map my design but I meet some trouble, the error message is :
ERROR:Pack:679 - Unable to obey design constraints
(LUTNM=I_FPGA/I_ITF_DSP2/ITF_PPI_0/___XLNM___2122___FiFo_Out_Data_In_Valid_mu
x000111) which require the combination of the following symbols into a single
SLICE component:
LUT symbol "I_FPGA/I_ITF_DSP2/ITF_PPI_0/FiFo_Out_Data_In_Valid_mux000111"
(Output Signal = I_FPGA/I_ITF_DSP2/ITF_PPI_0/FiFo_Out_Data_In_Valid_mux0001)
LUT symbol "I_FPGA/I_ITF_DSP2/ITF_PPI_0/FiFo_Out_Data_In_not00011" (Output
Signal = I_FPGA/I_ITF_DSP2/ITF_PPI_0/FiFo_Out_Data_In_not0001)
Function generators
I_FPGA/I_ITF_DSP2/ITF_PPI_0/FiFo_Out_Data_In_Valid_mux000111 and
I_FPGA/I_ITF_DSP2/ITF_PPI_0/FiFo_Out_Data_In_not00011 are not compatible. The
two function generators can not share a LUT site. Please correct the design
constraints accordingly.
According to this message, I must correct my contraints file in order to separate both functions.
First solution seems to consist in using the LOC contraint command but it implies to know where these LUT must be localise.
I would like to know what is the command to use to realize this separation without using the LOC command.
Thanks
