04-20-2012 01:59 AM
I try to map my design but I meet some trouble, the error message is :
ERROR:Pack:679 - Unable to obey design constraints
x000111) which require the combination of the following symbols into a single
LUT symbol "I_FPGA/I_ITF_DSP2/ITF_PPI_0/FiFo_Out_Data_In_Vali
(Output Signal = I_FPGA/I_ITF_DSP2/ITF_PPI_0/FiFo_Out_Data_In_Valid
LUT symbol "I_FPGA/I_ITF_DSP2/ITF_PPI_0/FiFo_Out_Data_In_not0
Signal = I_FPGA/I_ITF_DSP2/ITF_PPI_0/FiFo_Out_Data_In_not00
two function generators can not share a LUT site. Please correct the design
According to this message, I must correct my contraints file in order to separate both functions.
First solution seems to consist in using the LOC contraint command but it implies to know where these LUT must be localise.
I would like to know what is the command to use to realize this separation without using the LOC command.