New Users Forum

[hupaa]

What is the clock frequency?

50Mhz, like the frequency of first_counter.

[eteam00]

What is the clock frequency?

50Mhz, like the frequency of first_counter.

At 50MHz, 'all LEDs on and not counting' is certainly indistinguishable to the human eye from 'counting very fast'.

-- Bob Elkind

[hupaa]

this can't be the true simulation of your source

Yes, My simulation code is different from the code for actual hardware.

In simulation code I have defined a process for clock generation in TestBench, So I have deleted prescaler signals.

Also, in the count_test1 source you are not setting the prescaler back to zero when incrementing the conter.

Thanks, I do that.

Prescaler signal that shows the clock frequency has an equal value in 2 "count_test0" and "count_test1" and equal to 50Mhz.

[hupaa]

Also, in the count_test1 source you are not setting the prescaler back to zero when incrementing the conter.

after I have added ,prescaler <= (others => '0'),  Second counter began to counting. but when first_counter and second_counter counting together the first counter counting until 7, like a 3bits counter.

This Image shows the operation of count_struct.

[rcingham]

"Yes, My simulation code is different from the code for actual hardware."

And how is that useful?

[hupaa]

"Yes, My simulation code is different from the code for actual hardware."

And how is that useful?

difference between them is only in the frequency definition part, because in the code with "prescaler" I cant get output wave from my code and in fact counter does not counting.

I have attached my simulation file.

[eteam00]

hupaa,

Communicating effectively in an online user forum is not easy.  The difficulty is increased considerably with a language translation barrier which obscures clear ideas and descriptions.  A concerted effort is required.

After 16 or so posts to this thread, I am still unsure

• what is the behaviour you desire
• what is the behaviour you are observing

For example, you showed us a function sequence (of sorts) in post #14, but you did not specify whether this was the intended behaviour or the problem behaviour.

Are there 3 sets of design to be compared and reconciled?

• Intended design
• Simulated design
• Actual hardware design

Or are there only 2 sets of design to be compared and reconciled?

When you present data in your posts, please try add a better description of what the data represents, and how the data was gathered.

-- Bob Elkind

[hupaa · Accepted solution]

My problem has resolved.

I have attached the correct code. I have added a d_flipflop with enable port to save value of "sel" signal, so after the first time f_counter counting until 15, two counters counting together  until reset sets.

eteam00, the image of post 14 shows the operation of  count_struct after my code has changed a little and the image in post 5 shows what I want.

because I can not describe clearly what I want I have added Images.

Thanks for guidance.