New Users Forum

[2shy]

Hello, I have a problem with PS2 keyboard interface controller I'm trying to implement in Verilog. I have doubts about my two bidirectional ports, PS2 clock and PS2 data.

My top module is zad5 that includes a proper host PS2 module. Data incoming from keyboard is processed in hostPS2. HostPS2 also handles the transmission from host to keyboard (e.g. setting keyboard's LEDs) - by pulling wires ps2_clk_o and ps2_data_o low (as they are enabling signals in tri-state buffers ps2clk and ps2data and come from hostPS2 module).

To be honest, I have no idea, if my wiring is okay. I read a lot about PS2 interface and found out, that data and clock lines are 'open collector' type, so the transmission from host to keyboard should be driven using tri-state buffers. I also wanted to create a testbench for my top module. I have a problem in generating the clock and data signal (as the keyboard does), because the compiler gives lots of errors like these:

ERROR:HDLCompiler:731 - "zad5_test.v" Line 39. Procedural assignment to a non-register ps2_clk_io is not permitted ERROR:HDLCompiler:731 - "zad5_test.v" Line 40. Procedural assignment to a non-register ps2_data_io is not permitted

I'm guessing there is something wrong with my bidirectional ports. I'll be happy if anyone could help, I'm at the beggining of my adventure with HDL languages. Here's my code:

module zad5(clk_i, rst_i, ps2_clk_io, ps2_data_io);

input clk_i, rst_i; inout ps2_clk_io, ps2_data_io;

wire ps2_data_o;

wire ps2_clk_o;

hostPS2 h(.clk_i(clk_i), .KBDclk_i(ps2_clk_io), .KBDdata_i(ps2_data_io), .reset_i(rst_i), .KBDclk_en_o(ps2_clk_o), .KBDdata_en_o(ps2_data_o));

bufif0 ps2clk(ps2_clk_io, 1'b0, ps2_clk_o);

bufif0 ps2data(ps2_data_io, 1'b0, ps2_data_o);

endmodule

module hostPS2(clk_i, KBDclk_i, KBDdata_i, reset_i, KBDclk_en_o, KBDdata_en_o);

input clk_i, reset_i;

input KBDclk_i, KBDdata_i; //should be inout, or just input?

output reg KBDclk_en_o = 1'b1;

output reg KBDdata_en_o = 1'b1;

always@(posedge clk5MHz_i or posedge reset_i)

begin

//some code here

end

endmodule

[eteam00]

Hello, I have a problem with PS2 keyboard interface controller I'm trying to implement in Verilog. I have doubts about my two bidirectional ports, PS2 clock and PS2 data.

In the ISE Navigator shell, click on the lightbulb icon.  This opens the Language Templates window.  In these templates you will find coding examples for many constructs, including bidirectional IOs.  Here is the example you will find:

inout <top_level_port>;
wire <output_enable_signal>, <output_signal>, <input_signal>;
assign <top_level_port> = <output_enable_signal> ? <output_signal> : 1'bz;
assign <input_signal> = <top_level_port>;

From your post:

ERROR:HDLCompiler:731 - "zad5_test.v" Line 39. Procedural assignment to a non-register ps2_clk_io is not permitted ERROR:HDLCompiler:731 - "zad5_test.v" Line 40. Procedural assignment to a non-register ps2_data_io is not permitted

I'm guessing there is something wrong with my bidirectional ports. I'll be happy if anyone could help, I'm at the beggining of my adventure with HDL languages. Here's my code:

Two problems:

• You don't mark which lines are line 39 and line 40.  Duh!
• You don't include the code for module bufif0

Maybe your coding syntax for a bidi signal is the only problem.  See if applying the template form works.

-- Bob Elkind

[2shy]

Well, thanks for reply. I'll try with a template.

My testbench looks like this (there are ports for 7seg display, too, but I skipped them in previous code):

`timescale 1ns / 1ps

module zad5_test;

// Inputs
reg clk_i;
reg rst_i;

// Outputs
wire [3:0] led7_seg_an;
wire [7:0] led7_seg_o;

// Bidirs
wire ps2_clk_io;
wire ps2_data_io;

// Instantiate the Unit Under Test (UUT)
zad5 uut (
.clk_i(clk_i),
.rst_i(rst_i),
.led7_seg_an(led7_seg_an),
.led7_seg_o(led7_seg_o),
.ps2_clk_io(ps2_clk_io),
.ps2_data_io(ps2_data_io)
);


always
begin
#10 clk_i = ~clk_i;
end



initial begin
clk_i = 1'b0;

ps2_clk_io = 1;
ps2_data_io = 1;
rst_i = 1;
#1000;
rst_i = 0;

#70000 ps2_data_io = 0; //start bit
#16500 ps2_clk_io = 0;

#33000 ps2_clk_io = 1;
#16500 ps2_data_io = 0; //bit 0
#16500 ps2_clk_io = 0;

#33000 ps2_clk_io = 1;
#16500 ps2_data_io = 0; //bit 1
#16500 ps2_clk_io = 0;

#33000 ps2_clk_io = 1;
#16500 ps2_data_io = 0; //bit 2
#16500 ps2_clk_io = 0;

#33000 ps2_clk_io = 1;
#16500 ps2_data_io = 1; //bit 3
#16500 ps2_clk_io = 0;

#33000 ps2_clk_io = 1;
#16500 ps2_data_io = 1; //bit 4
#16500 ps2_clk_io = 0;

#33000 ps2_clk_io = 1;
#16500 ps2_data_io = 1; //bit 5
#16500 ps2_clk_io = 0;

#33000 ps2_clk_io = 1;
#16500 ps2_data_io = 0; //bit 6
#16500 ps2_clk_io = 0;

#33000 ps2_clk_io = 1;
#16500 ps2_data_io = 0; //bit 7
#16500 ps2_clk_io = 0;

#33000 ps2_clk_io = 1;
#16500 ps2_data_io = 0; //parity bit
#16500 ps2_clk_io = 0;

#33000 ps2_clk_io = 1;
#16500 ps2_data_io = 1; //stop bit
#16500 ps2_clk_io = 0;
#33000 ps2_clk_io = 1;


end



endmodule




As far as I remember from course, in Verilog bufif0 is a primitive, like NAND or NOR gate and stands for tri-state buffer, active low enable. Am I wrong? I don't have any code for this module.

[eteam00]

As far as I remember from course, in Verilog bufif0 is a primitive, like NAND or NOR gate and stands for tri-state buffer, active low enable. Am I wrong?

You are correct.  This is the first I've noticed this, for which I thank you!

-- Bob Elkind