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Newbie
polly
Posts: 1
Registered: ‎04-30-2012
0

WARNING:Xst:647

Dear All,

Need some advice, I’m fairly new to this. I’m using an xc65108 chip to control some fairly simple things, programming in ISE 13.1 This is my dilemma:

In the entity top_level I’ve declare an in signal, further down in the “architecture Behavioral of top_level” I read the signal in an if loop. When I compile the code I get the following warning

“WARNING:Xst:647 - Input <BIT_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.”

 

How do I get the code to understand that the signal is being used? What am I doing wrong?  I do something similar with another signal declared and used in an if loop, but it does not give me any warnings there. Do I have to declare it in another form? Any input will be greatly appreciated because I’ve gone blind here and can’t see the problem. Thank you!

 

/Polly

 

 

Example


Entity :

BIT_1 : in  STD_LOGIC;  

STATUS_5V : in  STD_LOGIC;

STATUS_1      : inout STD_LOGIC;

STATUS_2      : inout STD_LOGIC;

RADAR_OK : inout STD_LOGIC;

 

Behavioral:

--this code doesn’t generate warnings

 

process (STATUS_5V, R_OK)

            begin

                        if (STATUS_5V = '1') then

                                    R_OK <= '0';

                        else

                                    R_OK <= '1';

                                               

                        end if;

end process;

 

 

--this gives me the WARNING: Xst:647

 

process (BIT_1, STATUS_1, STATUS_2)

            begin

                        if (BIT_1 = '1') then

                                    STATUS_1 <= '1';

                        else

                                    STATUS_2 <= '1';

                                               

                        end if;

end process;

Expert Contributor
eteam00
Posts: 7,505
Registered: ‎07-21-2009
0

Re: WARNING:Xst:647

[ Edited ]

I can barely read VHDL, so I cannot comment on VHDL syntax issues.  Here are some other suggestions to solve your immediate problem:

 

  1. Cast STATUS_1 and STATUS_2 as output rather than inout, until you have use for these signals as inout.
  2. Add logic which assigns '0' to STATUS_1 and STATUS_2.  The synthesiser has no reason to infer that STATUS_1 and STATUS_2 can ever assume a '0' level, regardless of the state of input BIT_1.  If BIT_1 does not affect any other variables or signals, then BIT_1 has no use in the synthesised logic.  Hence the "never used" warning.

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

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Expert Contributor
rcingham
Posts: 2,010
Registered: ‎09-09-2010

Re: WARNING:Xst:647

"What am I doing wrong?"

Trying to use a language you do not understand.
Buy a book or do a course.

------------------------------------------
"If it don't work in simulation, it won't work on the board."