New Users Forum

[nigong]

Hi all,

I am a C programmer and new to VHDL.

Currently I am just teaching myself and practising VHDL on Spartan 3, XC3S1000.

Because I am from C, when I came across some really, really simple compiler errors, I have no idea of what the problem is at all.

Like this peice of code. I just want to set a output pin (NMIControl) into 1 when PB1 is falling edge. Otherwise sets NMIControl into 0. This is a very, very simple design but I totally don't know why the compiler doesn't like it. It says :

"

Signal NMIControl cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current
software release.

"

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity NMIControl is
	port (
		--CLK : in std_logic;
		PB1 : in std_logic;
		NMIControl : out std_logic;
		LED8 : out std_logic
	);
end NMIControl;

architecture Behavioral of NMIControl is
begin
	
	process (PB1)
	begin
		LED8 <= not PB1;
		if falling_edge (PB1) and PB1 = '0' then
			NMIControl <= '1';
		else 
			--if rising_edge (PB1) and PB1 = '1' then
				NMIControl <= '0';
			--end if;
		end if;
		
	end process;

end Behavioral;

I really don'y know what to do. Please help... 

Thanks

Ashley

[eteam00]

I just want to set a output pin (NMIControl) into 1 when PB1 is falling edge. Otherwise sets NMIControl into 0. This is a very, very simple design but I totally don't know why the compiler doesn't like it.

On what basis do you understand this function to be "very, very simple"?  It might be simple when sequentially executed in software -- detect an edge, set a bit, then flip the bit off again -- but you are designing hardware rather than software.

The problem is that you are describing something which does not exist in FPGA hardware.  There is no component which changes state on the edge of an input, and then immediately changes state again.

This is not a problem with understanding VHDL or the synthesiser, this is a problem with understanding FPGA hardware (in general) and (more specifically) registers.

You can describe almost anything you want, no matter how bizarre or outlandish, and a simulator will try to mimic the behaviour described by your code.  But that all stops when you map your code to actual hardware.  If you try to describe something which does not (or cannot) exist in the target device, the synthesiser simply cannot invent new hardware circuits to fit your code description.

So...  learn how FPGA registers work.  Do you have Document Navigator installed?  DocNav can help you find helpful information quickly and efficiently.  From the New Users Forum README thread:

For most current software and device families, Xilinx provides a software tool for finding and accessing useful documents.  This tool is called DocNav (Document Navigator), it installs on your PC, and you can download it with this .ZIP file link.

The range of documents covered by DocNav do not extend to the Spartan 3 device families, but understanding the workings of FPGA registers (and example source code for inferring registers) is a general subject which applies (nearly) identically to all of the Xilinx FPGA device families.  And, of course, the design tools (and user guides) covered by DocNav are the same design tools used for developing Spartan-3 designs.

Also from the same README thread:

Design skills:

I'm a beginner with FPGA designs - where do I start?  Online training tutorials and more:  link#1   link#2   thread#1  thread#2   thread#3 

A blog site for non-FPGA types learning about FPGAs

Back to your example --  is the following a reasonable re-formulation of your intended function?

• Detect the rising edge of an input (PB1)
• Set the register bit to '1' on the next clock edge.
• After some delay (1 clock cycle, for example) -- or perhaps without delay -- set the register bit back to 0 on the next clock edge.

In this example, a positive edge on the PB1 input will result in a short, defined output pulse.  This would be simple to implement with FPGA logic.

-- Bob Elkind

[bassman59]

Two suggestions:

a) Forget everything you know about C programming, as it is irrelevant to FPGA design.

b) Take a course in digital logic design, because that is exactly what you do when you do FPGA design.

[nigong]

Hi Bob, 

Thanks for your explanations and suggestions. They are very helpful. I KNOW VHDL is Hardware Description Language, but I think I don't UNDERSTAND what it means. Probably, it is describing the hardware which can realize your logic, but not only the logic...

---

Back to your example --  is the following a reasonable re-formulation of your intended function?

• Detect the rising edge of an input (PB1)
• Set the register bit to '1' on the next clock edge.
• After some delay (1 clock cycle, for example) -- or perhaps without delay -- set the register bit back to 0 on the next clock edge.

In this example, a positive edge on the PB1 input will result in a short, defined output pulse.  This would be simple to implement with FPGA logic.

---

You are right. That's what I want to implement. Could you give me a sample code? 

Thanks!

[eteam00]

Could you give me a sample code?

Verilog:

reg [1:0]  PB_dly=0; // synchronise and delay asynchronous PB input

reg out_pulse = 0;  // output pulse register

always @(posedge clock)

  PB_dly <= {PB_dly[0], PB_input};  // synchronise and delay asynchronous PB input

always @(posedge clock)

  out_pulse <= (PB_dly[0] & ~PB_dly[1]); // single-cycle pulse when PB rising edge detected

I don't have enough expertise to publish a VHDL version.

-- Bob Elkind

[eteam00]

I KNOW VHDL is Hardware Description Language, but I think I don't UNDERSTAND what it means.

It's one thing to learn VHDL or Verilog.  It is an entirely different matter to learn hardware logic design.  How are you going to learn hardware?  Are you going to enroll in a study course, as bassman suggested?

-- Bob Elkind

[eilert]

Hi,

The point with HDLs is:

You can SIMULATE almost any code that comes to your mind, if syntactically correct.

But for SYNTESIS the code has to comply to some extra rules, so it becomes possble to create some hardware representation of it.

If you want to face some similar situation with C: Try to do some professional real time programming. There are special rules that need to be followed to make this a save approach, and similar to synthesis only a subset of the language (or standard library functions) is allowed to be used. 

For VHDL theres part 4 of the IEEE standard, explaining what is allowed and possible for synthesis.

Some simple hints can be found in the ISE language templates which have a special section for synthesis.

Also, in order to know what can be described with a HDL one needs to know about digital hardware structures. Mainly the basic circuit design, but some knowledge about the specific target architecture (e.g. FPGAs) is also very beneficial.

Have a nice synthesis

  Eilert