New Users Forum

[tayeb]

Hi,

I am traying to add a customized IP the Microblaze system and don't know how to connect the clock of my IP to the clk_syst of virtex-6 fpga.

Can anybody help me to resolve this problem please

Thanks

[austin]

t,

The signal name you need to declare is not the name of the signal at the pin, but the name of the signal at the OUT port of the BUFG.

I believe you can find this by looking in the .mhs file (it has been awhile since I did this).

In any event, you may also add a clock generator to your EDK project, and generate a different clock (different frequency, or phase) if you need to.

Also look for the signal names in the project, under the existing clock generator.  Again, you need the name at the output of the BUFG.

[tayeb]

Iam traying to add output clock for clock_generator to generate the clock, but I can not configure it!!! I mean I can not add an other clock output

[austin]

t,

You may be at the maximum number of outputs, which means you need to add another clock generator module, in parallel with the first one, to provide more outputs.

Or, the frequency you have chosen for your output is not possible to be synthesized.

[tayeb · Accepted solution]

Hi

I managed to add another clockout of clock_generator without adding another paralel clock_generator, but directely with adding a second clouk output in system.mhs

[austin]

t,

Congratulations!  I know how hard this is to do, as I had to do it also.  It seems like it should be easier to accomplish, but the devil is in the details.  Just one spelling error, or forgeting to change just one file, is all it takes to not work...

[tayeb]

thanks austin :)