New Users Forum

[cookjw2]

Yes I am a newbie, new to ISE, new to CPLDs and new to verilog.  I am not new to electronics or logic though, but my previous professional experience tended to be a bit more discrete and hands-on!  I hope to learn something from the answer to this question, as I'm very puzzled by what I am experiencing.

This is only my second PLD design, and it was going very well.  The design processes a serial input and has just 5 serial outputs too, so it is not at all I/O intensive.  I had pretty much completed the design, fitting it into an XC2C64A CPLD, with the following fit summary:

Macrocells Product Terms Function Block Registers Pins

Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot

41 /64 ( 64%) 166 /224 ( 74%) 95 /160 ( 59%) 25 /64 ( 39%) 14 /33 ( 42%)

The design was verified with iSim.  To make this quicker during the design I had routed the state (7-bits) of the main internal state machine to outputs, as this makes iSim immediately make them available for view without having to fiddle with the GUI.

Having completed the design I decided to disconnect these outputs.  All I did to do this was to delete "state" from the module's parameter list, and delete the corresponding output declaration, leaving the register declaration intact (the design is contained in a single verilog file).

After this edit there is no syntax error and the synthesize and translate phases pass without incident.

However the fitting fails catestrophically:

************************** Errors and Warnings ***************************

ERROR:Cpld:1063 - Design requires at least 123 macrocells, exceeds device limit

64.

ERROR:Cpld:1062 - Design contains 322 unique product terms, exceeds device limit

224.

ERROR:Cpld:1064 - Design rules checking error. Fitting process stopped.

ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with

the selected implementation options.

************************* Mapped Resource Summary **************************

No logic has been mapped.

Macrocells Product Terms Function Block Registers Pins

Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot

0 /64 ( 0%) 0 /224 ( 0%) 0 /160 ( 0%) 0 /64 ( 0%) 0 /33 ( 0%)

I am at a loss to understand the significance of the change I have made.

Having read some of the posts in this forum, I have tried changing the fitting objective between density and speed, but this makes no material difference.  With either setting the design fits with the extra outputs connected but does not fit with the outputs disconnected.

For the record my ucf file is currently empty; I'm constraining nothing.

Obviously I have an easy solution to my problem: just leave the unused "state" bits connected to output pins.

But I would very much like to understand what is going on; I'm sure it will make me a better user.

Thanks for reading...

[gszakacs · Accepted solution]

I was not aware of this problem on CPLD's, but at least for FPGA's the standard FSM implementation

re-encodes your state variable as "one-hot", meaning that if you had 16 states, instead of 4 state

registers you would have 16.  In an FPGA which has flip-flops to spare, this makes a lot of sense.

I don't see the point of using one-hot in a CPLD.  You may want to look through the synthesis

options and look for "FSM encoding."  If this option exists for CPLD's make sure to set it to

"user" rather than "auto" or "one-hot."

-- Gabor

[cookjw2]

Thanks Gabor for you input.  I made the change you suggested and Voila!, it does the trick.  Fitting now yeilds exactly the same results as it did with the outputs connected.

I will study this setting and try to understand it better.

John