New Users Forum

[tayeb]

Hi,

I'm looking for someone who has already connected its own IP on the PLB bus with FIFO for he shares his experience with me, for me it's been a month since I tried to do unsuccessfully

I would like to have an exemple user_logic file where we connect our IP to the PLB interface with fifos

thanks

[tayeb]

my user_logic.vhd:

architecture IMP of user_logic is

--USER signal declarations added here, as needed for user logic

------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg4 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg5 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 5);
signal slv_reg_read_sel : std_logic_vector(0 to 5);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;

------------------------------------------
-- Signals for read/write fifo loopback example
------------------------------------------
type FIFO_CNTL_SM_TYPE is (IDLE, RD_REQ, WR_REQ);
signal fifo_cntl_ns : FIFO_CNTL_SM_TYPE;
signal fifo_cntl_cs : FIFO_CNTL_SM_TYPE;
signal fifo_rdreq_cmb : std_logic;
signal fifo_wrreq_cmb : std_logic;
--------------------------------------------------------------
--User signals

signal slv_reg0_sig : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1_sig : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2_sig : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3_sig : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg4_sig : std_logic_vector(0 to C_SLV_DWIDTH-1);

--Declaration de ASEPA
component asepa_v3
port ( clk_bus : in std_logic;
data_in : in std_logic_vector (0 to 15);
dv : in std_logic;
inf_f1 : in std_logic_vector (0 to 15);
inf_f2 : in std_logic_vector (0 to 15);
inf_f3 : in std_logic_vector (0 to 15);
rcs : in std_logic_vector (0 to 15);
rst_sys : in std_logic;
rtm : in std_logic_vector (0 to 15);
seuil_div : in std_logic_vector (0 to 15);
sup_f1 : in std_logic_vector (0 to 15);
sup_f2 : in std_logic_vector (0 to 15);
sup_f3 : in std_logic_vector (0 to 15);
taille_ascan : in std_logic_vector (0 to 15);
alarme1 : out std_logic_vector (0 downto 0);
alarme2 : out std_logic_vector (0 downto 0);
alarme3 : out std_logic_vector (0 downto 0);
numero_ascan : out std_logic_vector (0 to 7);
read_ack : out std_logic_vector (0 downto 0));
end component;

begin

--USER logic implementation added here
instance: asepa_v3
port map (clk_bus =>Bus2IP_Clk,
data_in =>WFIFO2IP_Data(16 to 31),--fifo ---->IP
DV =>RFIFO2IP_WrAck ,
inf_f1 =>slv_reg0_sig(16 to 31),
inf_f2 =>slv_reg1_sig(16 to 31),
inf_f3 =>slv_reg2_sig(16 to 31),
RCS =>slv_reg4_sig(16 to 31),
rst_sys =>Bus2IP_Reset,
RTM =>slv_reg4_sig(0 to 15),
seuil_div =>slv_reg3_sig(0 to 15),
sup_f1 =>slv_reg0_sig(0 to 15),
sup_f2 =>slv_reg1_sig(0 to 15),
sup_f3 =>slv_reg2_sig(0 to 15),
taille_ascan =>slv_reg3_sig(16 to 31),
numero_ascan =>IP2RFIFO_Data(24 to 31),
alarme1 =>IP2RFIFO_Data(22 to 22),
alarme2 =>IP2RFIFO_Data(21 to 21),
alarme3 =>IP2RFIFO_Data(20 to 20),
read_ack =>IP2RFIFO_Data(23 to 23)
);
--
slv_reg0_sig<=slv_reg0;

slv_reg1_sig<=slv_reg1;

slv_reg2_sig<=slv_reg2;

slv_reg3_sig<=slv_reg3;

slv_reg4_sig<=slv_reg4;--rcs --rtm

------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 5);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 5);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5);

-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
else
case slv_reg_write_sel is
when "100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;

end process SLAVE_REG_WRITE_PROC;

-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5 ) is
begin

case slv_reg_read_sel is
when "100000" => slv_ip2bus_data <= slv_reg0;
when "010000" => slv_ip2bus_data <= slv_reg1;
when "001000" => slv_ip2bus_data <= slv_reg2;
when "000100" => slv_ip2bus_data <= slv_reg3;
when "000010" => slv_ip2bus_data <= slv_reg4;
when "000001" => slv_ip2bus_data <= slv_reg5;
when others => slv_ip2bus_data <= (others => '0');
end case;

end process SLAVE_REG_READ_PROC;

------------------------------------------
-- Example code to transfer data between read/write fifo
--
-- Note:
-- The example code presented here is to show you one way of operating on
-- the read/write FIFOs provided for you. There's a set of IPIC ports
-- dedicated to the FIFO operations, beginning with RFIFO2IP_* or IP2RFIFO_*
-- or WFIFO2IP_* or IP2WFIFO_*. Some FIFO ports are only available when
-- certain FIFO services are present, s.t. vacancy calculation, etc.
-- Typically you will need to have a state machine to read data from the
-- write FIFO or write data to the read FIFO. This code snippet simply
-- transfer the data from the write FIFO to the read FIFO.
------------------------------------------
IP2RFIFO_WrMark <= '0';
IP2RFIFO_WrRelease <= '0';
IP2RFIFO_WrRestore <= '0';

IP2WFIFO_RdMark <= '0';
IP2WFIFO_RdRelease <= '0';
IP2WFIFO_RdRestore <= '0';

FIFO_CNTL_SM_COMB : process( WFIFO2IP_empty, WFIFO2IP_RdAck, RFIFO2IP_full, RFIFO2IP_WrAck, fifo_cntl_cs ) is
begin

-- set defaults
fifo_rdreq_cmb <= '0';
fifo_wrreq_cmb <= '0';
fifo_cntl_ns <= fifo_cntl_cs;

case fifo_cntl_cs is
when IDLE =>
-- data is available in the write fifo and there's space in the read fifo,
-- so we can start transfering the data from write fifo to read fifo
if ( WFIFO2IP_empty = '0' and RFIFO2IP_full = '0' ) then
fifo_rdreq_cmb <= '1';
fifo_cntl_ns <= RD_REQ;
end if;
when RD_REQ =>
-- data has been read from the write fifo,
-- so we can write it to the read fifo
if ( WFIFO2IP_RdAck = '1' ) then
fifo_wrreq_cmb <= '1';
fifo_cntl_ns <= WR_REQ;
end if;
when WR_REQ =>
-- data has been written to the read fifo,
-- so data transfer is done
if ( RFIFO2IP_WrAck = '1' ) then
fifo_cntl_ns <= IDLE;
end if;
when others =>
fifo_cntl_ns <= IDLE;
end case;

end process FIFO_CNTL_SM_COMB;

FIFO_CNTL_SM_SEQ : process( Bus2IP_Clk ) is
begin

if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
IP2WFIFO_RdReq <= '0';
IP2RFIFO_WrReq <= '0';
fifo_cntl_cs <= IDLE;
else
IP2WFIFO_RdReq <= fifo_rdreq_cmb;
IP2RFIFO_WrReq <= fifo_wrreq_cmb;
fifo_cntl_cs <= fifo_cntl_ns;
end if;
end if;

end process FIFO_CNTL_SM_SEQ;

--IP2RFIFO_Data <= WFIFO2IP_Data;

------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');

IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';

end IMP;