05-12-2012 06:28 AM
I have the Xilinx XUPV5-LX110T Evaluation Platform, now i want to analyze the output signal from FPGA with LA(Logic Analyzer).
But i do not know which part of Evaluation Platform the LA should connect to.
Solved! Go to Solution.
05-13-2012 07:53 AM
In your design, you assign the signals of intest to be routed to IO pins. You choose the IO standard you wish, and place them on an IO bank which connects to the pins of the connector on the board (to the right-hand side). Examine the schematics to choose the pins for the connector, and tthe IO pin names for your VHDL, or verilog coding. Then connect the LA to these pins.
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