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how to design wave pipelined fir filter
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05-20-2012 07:55 AM
hi some one please tell me how to design wave pipelined fir filter using vhdl .
Re: how to design wave pipelined fir filter
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05-21-2012 05:34 AM
Hm, what is a "wave" pipelined FIR filter?
A pipelined filter has to be more or less a parallel filter, depending on the pipeline data speed.
Case1: Total Serial
All coefficients are processed one after another and you will get a data speed of N = 1 / k (k = no of coeffs) because you feed data into the input and calculated one filter coeff per clock cylce.
Case 2: Partial Serial and Parallel
Some Coefficients are mapped together in a e.g. two stage filter design. Filter Coeffs are mosty mirrored (in 2 D filters twice having 4 quadrants). Additionally you can calculate several coefficients in parallel using parallel MUL-architecture.
Case 3: Full Parallel
All coeffs are multiplied with their corresponding data elements in parallel. You can feed new data every clock cylce. You can select to shun embedded multipliers for some designs to give the synthesis a chance to search for redundancy in the coeffs and architecture.
In most cases, CASE 3 does not make sense, because you might not want to process a wave for every shifted sample.
For audio for example, you can process an incoming 192kHz wave with a 1024 TAP filter fully in serial using around 200MHz Clock Speed. for observation and analysis of more then one channel and also longer filters, you can process the wave like this:
1. Sample 0 to Sample 8191
2. Sample 16 to Sample 8191 + 16
3. Sample 32 to Sample 8191 + 32
and so on.
So You will have 16 channels to process with only one architecture. Of course the result is more coarse and is somehow distorted in the hight bands. But often this is suitable since, during processing, you might have to apply windowing anyway which causes distorsion too.
Re: how to design wave pipelined fir filter
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05-22-2012 05:47 PM
Perhap the OP is referring to a systolic (or similar ) filter? A fully parallel filter where the data at each stage (tap) of the filter is shifted in time - because of the pipeline delays. I've heard the term "wave" before used to describe this.
Check the "XtremeDSP for Virtex-4 FPGAs User Guide (UG073)" Yes, it's an older technology - but the writeup here is better than the newer techs, and it still applies. See pg 82. "Systolic FIR Filter" section
I often need to create a spreadsheet when designing these filters to get the pipeline delays correct.
Use the columns in the spreadsheet to represent advancing time, and have each stage of the filter
on another row. You can kindof see the wave...
--Mark











