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Regular Visitor
glxidian
Posts: 31
Registered: ‎10-19-2011
0
Accepted Solution

ml_605 DCI

In the schematics of ml_605,i found in a bank(for example bank 16)which was mixed LVDS signals and signle-end signals ,so the bank should be constrianed lvds 2.5v , and the bank had a DCI match.However in the bank 24(the bank was mixed LVDS signals and signle-end signals),so the bank should be constrianed lvds 2.5v also,the bank did not have DCI match. That's why? What's the differences between these two confiditions .I  had known that using the DCI match can increase the integrity of signal.But I was fused when i should slect a DCI or not(use the pins VRN and VRP as DCI match or not).

Xilinx Employee
austin
Posts: 3,870
Registered: ‎02-27-2008
0

Re: ml_605 DCI

DCI is a feature that has nothing to do with LVDS.

 

It is for other standards, Like LVDCI LVCMOS, and SSTL and HSTL DCI modes.

Austin Lesea
Principal Engineer
Xilinx San Jose
Regular Visitor
glxidian
Posts: 31
Registered: ‎10-19-2011
0

Re: ml_605 DCI

Dear Jose:
Thanks for you reply!
Expert Contributor
bassman59
Posts: 4,741
Registered: ‎02-25-2008
0

Re: ml_605 DCI


glxidian wrote:
Dear Jose:
Thanks for you reply!

Who is Jose?


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