New Users Forum

[aliaarshad]

hi,

i m trying to map the following source code

module clock_xx(clk_in,d_in,dout,douta,doutb,clk_out2);

 input clk_in; input [31:0] d_in;

output reg[31:0] dout;

output clk_out2;

output [7:0] douta,doutb;

reg[7:0]out1;

reg[7:0]out2;

 wire clk_out1;

 wire clk_out2;

clock_double1 a1(// Clock in ports     .CLK_IN1(clk_in),       .CLK_OUT1 (clk_out1), .CLK_OUT2 (clk_out2));      

always @ (posedge clk_out1 or negedge clk_out1)  

 if (clk_out1 == 0)  

 begin  

out1 <= d_in[7:0];  

out2 <= d_in[23:16];  

end  

else  

begin  

out1 <= d_in[15:8];  

 out2 <= d_in[31:24];  

 end  

memory_ROM bs (  .clka(clk_out2),  .addra(out1), // Bus [7 : 0]  .douta(douta), // Bus [7 : 0]  .clkb(clk_out2),  .addrb(out2), // Bus [7 : 0]  .doutb(doutb)); // Bus [7 : 0]    

always @ (posedge clk_out1 or negedge clk_out1)  

if (clk_out1 == 0)  

 begin  

dout[7:0] <= douta;  

dout[23:16] <= doutb;  

 end  

 else  

 begin  

dout[15:8] <= douta;  

dout[31:24] <= doutb;  

end   

endmodule

bt during mapping i get the following errors

ERROR:Place:1206 - This design contains a global buffer instance,    <a1/clkout2_buf>, driving the net, <clk_out2_OBUF>, that is driving the    following (first 30) non-clock source pins off chip.    < PIN: clk_out2.O; >    This design practice, in Spartan-6, can lead to an unroutable situation due    to limitations in the global routing. If the design does route there may be    excessive delay or skew on this net. It is recommended to use a Clock    Forwarding technique to create a reliable and repeatable low skew solution:    instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to    Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to    .C1. If you wish to override this recommendation, you may use the    CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote    this message to a WARNING and allow your design to continue. Although the net    may still not route, you will be able to analyze the failure in FPGA_Editor.    < PIN "a1/clkout2_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >

ERROR:Place:1136 - This design contains a global buffer instance,    <a1/clkout2_buf>, driving the net, <clk_out2_OBUF>, that is driving the    following (first 30) non-clock source pins.    < PIN: clk_out2.O; >    This is not a recommended design practice in Spartan-6 due to limitations in    the global routing that may cause excessive delay, skew or unroutable    situations.  It is recommended to only use a BUFG resource to drive clock    loads. If you wish to override this recommendation, you may use the    CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote    this message to a WARNING and allow your design to continue.    < PIN "a1/clkout2_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >

ERROR:Place:1136 - This design contains a global buffer instance,    <a1/clkout1_buf>, driving the net, <clk_out1>, that is driving the following    (first 30) non-clock source pins.    < PIN: Mmux_d_in[31]_d_in[23]_mux_3_OUT11.A3; >    < PIN: Mmux_d_in[31]_d_in[23]_mux_3_OUT31.A3; >    < PIN: Mmux_d_in[31]_d_in[23]_mux_3_OUT51.A3; >    < PIN: Mmux_d_in[31]_d_in[23]_mux_3_OUT71.A3; >    < PIN: Mmux_d_in[15]_d_in[7]_mux_2_OUT11.A3; >    < PIN: Mmux_d_in[15]_d_in[7]_mux_2_OUT31.A3; >    < PIN: Mmux_d_in[15]_d_in[7]_mux_2_OUT51.A3; >    < PIN: Mmux_d_in[15]_d_in[7]_mux_2_OUT71.A3; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT21.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT31.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT131.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT41.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT11.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT141.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT51.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT121.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT241.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT151.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT61.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT231.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT251.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT161.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT71.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT261.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT171.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT81.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT271.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT181.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT91.A5; >    < PIN: Mmux_doutb[7]_dout[31]_mux_8_OUT281.A5; >    This is not a recommended design practice in Spartan-6 due to limitations in    the global routing that may cause excessive delay, skew or unroutable    situations.  It is recommended to only use a BUFG resource to drive clock    loads. If you wish to override this recommendation, you may use the    CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote    this message to a WARNING and allow your design to continue.    < PIN "a1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >

Phase 2.7  Design Feasibility Check (Checksum:5ab9) REAL time: 13 secs

Total REAL time to Placer completion: 13 secs Total CPU  time to Placer completion: 10 secs ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

just wanted to map above source code in spartan-6, your quick response will be appreciated.

thanx

aliya

[austin]

Aliya,

Is this ASIC code?  What was it written for?  When you hasve RTL for a FPGAs device, you need to use the features of the FPGA to get the best (working) results.  That includes using the BUFG, DDR, etc. as required.  The synthesis tools are not smart enough to guess what to do, you have to map the code into the features of the device.

http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

(examples for S6, detailed above)

[eteam00]

Let's start with the basics...

1.  PLEASE when posting source code, use a fixed pitch font (e.g. Courier New) or the code insertion button (immediately right from the strikethrough font button).  This improves readability by leaps and bounds.

2.  Comments help readability as well.  My added comments are in red.

module clock_xx(clk_in,d_in,dout,douta,doutb,clk_out2);

 input clk_in; input [31:0] d_in;

 output reg[31:0] dout;

 output clk_out2;

 output [7:0] douta,doutb;

reg[7:0]out1;

reg[7:0]out2;

wire clk_out1;

wire clk_out2;

// NOTE:  the following line is broken syntax.

clock_double1 a1(// Clock in ports  .CLK_IN1(clk_in), .CLK_OUT1 (clk_out1), .CLK_OUT2 (clk_out2));

// Corrected with needed line breaks -- PLEASE POST CODE for this module

clock_double1 a1(// Clock in ports

.CLK_IN1(clk_in),

.CLK_OUT1 (clk_out1),

.CLK_OUT2 (clk_out2));

always @ (posedge clk_out1 or negedge clk_out1) // this cannot be synthesised to real FPGA hardware

 if (clk_out1 == 0)  

   begin  

     out1 <= d_in[7:0];  

     out2 <= d_in[23:16];  

   end  

 else  

   begin  

     out1 <= d_in[15:8];  

     out2 <= d_in[31:24];  

   end

// missing line breaks inserted -- PLEASE POST CODE for this module

memory_ROM bs (

.clka(clk_out2),

.addra(out1), // Bus [7 : 0]

.douta(douta), // Bus [7 : 0]

.clkb(clk_out2),

.addrb(out2), // Bus [7 : 0]

.doutb(doutb)); // Bus [7 : 0]

always @ (posedge clk_out1 or negedge clk_out1)  // this cannot be synthesised to real FPGA hardware

if (clk_out1 == 0)  

 begin  

   dout[7:0] <= douta;  

   dout[23:16] <= doutb;  

 end  

else  

 begin  

   dout[15:8] <= douta;  

   dout[31:24] <= doutb;  

 end   

endmodule

We can get specific about the error messages if the code for the memory_ROM and clock_double1 modules is posted.

-- Bob Elkind

[aliaarshad]

Hi,

Thnx for ur reply..

This prgram has been written to efficiently use dual port BRAM to obtain multiple copies of given data with dcm of double frequency. 

[eteam00]

This prgram has been written to efficiently use dual port BRAM to obtain multiple copies of given data with dcm of double frequency.

1.  This isn't a software program, it's a logic hardware description.

2.  If it does not synthesise to a working FPGA design, the efficiency of the design is of little practical use.

How can we help you?

-- Bob Elkind

[aliaarshad]

Hi.

The code has been attached for your assistance.

DCM and BRAMs are being instantiated using ip core generator in spartan 6, the given code has been written in xilinx 13.1 and successfully synthesized.

can u plz help me in mapping the code, 

thnx

ALIYA

[eteam00]

I prefer to review your source code rather than your .xise project file.

-- Bob Elkind