New Users Forum

[gourapatil]

Hi all

I am trying to design a 256 bytes of memory.

My target device is Virtex 5

I am using VIO and ILA from IP core generator debug and verification toolbox

i am getting an error "waiting for core to be armed, slow or stopped clock"

neither ILA is capturing waveforms nor VIO is giving any outputs.

please help me out

Thank u.

[rcingham]

"I am trying to design a 256 bytes of memory."

You don't need to. The CoreGen "Block Memory Generator" and "Distributed Memory Generator" tools do the work for you.

[gszakacs]

The error message is pretty descriptive.  Make sure that your clock is running and connected

to the clock input of the ILA and VIO blocks.  With no clock, ChipScope won't run.

-- Gabor