New Users Forum

[glxidian]

In virtex-6 fpga ,one bank(for example bank-36) is only constrianed at a level standard.If i constrain bank-36 at lvds 2.5v for differencial signal,can i connect one single-ended signal in that bank?

[austin · Accepted solution]

g,

Yes.  Once you choose the Vcco for a bank, then all IOs within that bank must then have compatible Vcco requirements.

Spartan 6 is not as strict, and allows some differences, while Virtex 6 does not.

Consult the IO Users Guide for all the Details

http://www.xilinx.com/support/documentation/user_guides/ug361.pdf

[glxidian]

Thank you for you reply!

[liejie04065136]

Hi Austin ,

      So one bank of virte-6 FPGA only use a level standard, but in the schematics of ml_605,i found in a bank(for example bank 16)which was mixed differential signals(for example LVDS) and signle-end signals(for example LVCMOS) ,what should i do ?When i constrian the bank with the level LVDS , can the signle-end signals work normally?

 Regards.

[austin]

Read my post again,

As long as the single ended IO uses the same Vcco in V6, then differential and single ended may reside in the same IO bank (as shown in the schematics you reference).

You will get an error if you can not instantiate the IO you wish, otherwise, with no error, it will work.

S6 is less strict, as the single ended inputs may be another voltage, and still be valid in the bank with the LVDS (again, read the users guide).