06-19-2012 06:54 AM
I have been trying to run a successful simulation with a x1 PCIe example design generated for a 7 Series device, but I have been unable to do so. I can get the simulation running (currently with TESTNAME = pio_writeReadBack_test0), but it never gets a link up status (i.e. /board/EP/user_lnk_up == 0 and /board/EP/user_reset == 1). It also never seems to time out (up to ~1.5 ms). I have perused through many prior reports of similar issues with earlier devices and previous software versions, but
I have not found any solutions.
The details of my environment are as follows:
ISE Version: 13.4
OS: Windows Vista 32-bit
Memory: 3 GB
Target Device: Kintex 7 (XC7K70T)
Core: 7 Series Integrate Block for PCI Express (version 1.3)
I'm new to using ISim. I've only recently started using it versus ModelSim SE. I started out trying to invoke the simulation from the ISE gui (via "Simulate Behavioral Model") and I have also tried invoking the simulation via simulate_isim.bat. Running from the .bat was more problematic with it failing in the absence of the isim_cmd.tcl file.
So... my first question is whether something stands out about this development environment that would prevent ISim from being able to run a PCIe simulation for a Kintex 7. I suspect I'm starting to push the system's limit for being able to handle the new devices (and actually my eventual design targets the xc7k325t of the KC705 board, but I've backed off the device to a XC7K70T to make some progress until we get our development machine replaced).
Secondly, are there any outstanding issues with the 7 Series PCIe core or support of Kintex 7s that would be causing my problems.
According to the known issues in AR# 40469, the candidate issues that sound related to my problems include:
-AR# 44732 - even though it called out VHDL, it did discuss Verilog in the description so I tried updating the fuse.exe parameters and tying the mentioned PIPE_ ports to 0 appropriately
-AR# 47316 - the "Important Note" makes this one sound like it it affects hardware only and simulation should be okay. However, in trying to add the missing connection anyway and explicitly set the mentioned parameters to 0 for simulation, I couldn't even locate the PCIE_OOBCLK_MODE parameter in any of the source files.
-AR# 43949 - should already be resolved for ISE 13.4 and core v1.3?
-AR# 41053 - should already be resolved for ISE 13.4 and core v1.3? (Verified that plllkdetWAS replaced with phystatus_rst in the phy_rdy_n assignment in _gt_top.v file.)
Any help with these difficulties would be greatly appreciated... I really need to make progress in simulating my custom designs, but need to understand why I can't even get the example designs to simulate successfully first.
06-19-2012 11:42 AM
The core doesn't seem to support isim yet.
06-20-2012 12:46 PM
Thanks for the reply!
When we started targeting a Kintex 7, we upgraded our development environment from ISE 11.2 to 13.4. Unfortunately, I was under the impression that we were able to start simulating everything exclusively with ISim and was not aware that it would vary on a core by core basis. The PCIe user guide (ug477) does mention ISim numerous times and the core generates an simulate_isim.bat script. (On a side note, I've also had problems with SGMII simulation, but I now see that its datasheet also does not list ISim as a supported simulator.)
Our ModelSim is old at version 6.5b (the compatible version published in ug631 - ISE 13: Release Notes Guide is 6.6d). I still gave our old version a try with the PCIe simulation, but ran into the same issues compiling the secureIP libraries that were reported here:
Our there any "unofficial" scripts to allow PCIe to be simulated with ISim as was described in these previous posts?