03-13-2012 12:17 AM - edited 03-14-2012 05:15 AM
I have EDK13.4 V6 project with AXI_PCIE (1.02.a), AXI_CDMA (3.02.a), AXI_V6_DDR (with DDR3).
Read DMA transaction initiated by AXI_CDMA (@simple mode) from PCIe (SBC memory) to local DDR3 works quite well (but not very fast aprox. 170MB/s for PCIE 4X gen 1).
On reverse direction (move data from local DDR3 to PCIe) CDMA stalls (doesn't finish operation), AXI_PCIE slave functionality for read access blocks (driver return 0xffffffff), but PCIe slave write access still works.
Could anybody tell about this issue?
Moreover what is maximum speed оf DMA transer for system based on AXI_PCIE bridge (PCIE 4X V6) and how to reach it?
03-13-2012 10:39 AM
Did you ensure that your CDMA transfer doesn't exceed the max payload size?
I'm working on a similar project. Do you mind telling me how you set up the host side device driver. How do you interrupt the host, when the DMA transfer is complete? Do we have to generate an MSI explicitly or will the bridge take care of it.?
03-14-2012 12:10 AM - edited 03-14-2012 12:11 AM
Same problem presents with small transfer size (8 byte / 16 byte) too.
At the moment SBC driver polls CDMA status (after some delay), but I plan to use interrupt too.
About int generation, bridge has this functionality (MSI_REQ input), so I will use it.
03-15-2012 08:03 AM
Sorry I can't solve your problem.
But I was going through your mhs file, I was curious as to what your util_vector_logic module does? Is it generating processor reset, when all clocks are stable. What is the logic, is it simply a NAND gate?
03-15-2012 05:05 PM
03-16-2012 02:05 AM - edited 03-16-2012 02:30 AM
No, BAR/link can't be missed since slave write operation via PCIe works (my MB programm every several seconds logs current value of several registers, including CDMA registers, and its value changes as write operation).
I connect AXI monitors to CDMA_M and axi_PCIe_S and during 64K block operation found that CDMA works correctly (read data DDR3, then write it to axi_pcie)
but axi_pcie "stall" data flow after first burst 0x40*4byte.
P.S. We got speed for DMA read operation near 500MB/s and question about speed expired.
03-16-2012 05:03 AM - edited 03-16-2012 06:22 AM
Unfortunately in provided early CDMA processing screenshot doesn't show several signal. When CDMA write to axi_pcie after burst BVALID signal has not a strobe,
but it has strobe when CDMA transfer data beetween two regions of ddr3.
As you can show at next picture axi_pcie doesn't assert bvalid when got written 256byte burst.
Could you tell about reason of this functionality?
03-19-2012 01:45 AM - edited 03-19-2012 01:48 AM
Please see axi_monitor shots with 48 byte cdma transfer size and bus checking signals: