PCI Express

[hse07013]

Hello,

I use the AXI PCIe Bridge 1.03.a. I tried to send and receive data (4 kiB) concurrently from/to the slave bridge with two seperate DMAs. Due to the implemented ordering, the bridge locks up. Both DMAs stop working when transmitted about 1 kiB. The axi interconnect is in crossbar mode. Destination and source IP-Cores are non-blocking and well-tested.

My work around is to disable the ordering in the axi_pcie_mm_s_v1_03_a/hdl/vhdl/slave_bridge.vhd:

	 -- Ordering signals
-      slave_read_req_p        => slrdready,
-      slave_rd_req_go         => slrdsend,
-      slave_cmpl_rdy_p        => slcplready,
-      slave_cmpl_go           => slcplsend,
-      slv_write_idle          => sig_slv_write_idle,
-      master_wr_idle          => master_wr_idle,

	 -- Ordering signals
+      slave_read_req_p        => slrdready,
+      slave_rd_req_go         => '0', --slrdsend,
+      slave_cmpl_rdy_p        =>  slcplready,
+      slave_cmpl_go           => '0', --slcplsend,
+      slv_write_idle          => '1', --sig_slv_write_idle,
+      master_wr_idle          => '1', --master_wr_idle,

Here is the microblaze test code to reconstruct the calling order of the DMAs:

	XAxiPcie_BarAddr BarAddr;
	BarAddr.LowerAddr = 0x60000000;
	BarAddr.UpperAddr = 0x00000000;	
	const u32 BytesToTransfer = 4096 * 4;
	u32 SrcAddr, DstAddr;

	/**
	 * Simple Mode from FPGA to Host
	 */
	SrcAddr = 0x30000000;
	DstAddr = 0xC0000000;

	PciePcieRegs[XAXIPCIE_AXIBAR2PCIBAR_0U_OFFSET / sizeof(u32)]
			= BarAddr.UpperAddr;
	PciePcieRegs[XAXIPCIE_AXIBAR2PCIBAR_0L_OFFSET / sizeof(u32)]
			= BarAddr.LowerAddr;

	PcieReadDmaRegs[XAXICDMA_CR_OFFSET / sizeof(u32)] = XAXICDMA_CR_RESET_MASK;
	PcieReadDmaRegs[XAXICDMA_CR_OFFSET / sizeof(u32)]
			= XAXICDMA_XR_IRQ_IOC_MASK | XAXICDMA_XR_IRQ_ERROR_MASK;

	PcieReadDmaRegs[XAXICDMA_SRCADDR_OFFSET / sizeof(u32)] = SrcAddr;

	PcieReadDmaRegs[XAXICDMA_DSTADDR_OFFSET / sizeof(u32)] = DstAddr;

	PcieReadDmaRegs[XAXICDMA_BTT_OFFSET / sizeof(u32)] = BytesToTransfer;

	/**
	 * Simple Mode from Host to FPGA
	 */
	SrcAddr = 0xE0000000;
	DstAddr = 0x40000000;

	PciePcieRegs[XAXIPCIE_AXIBAR2PCIBAR_2U_OFFSET / sizeof(u32)]
			= BarAddr.UpperAddr;
	PciePcieRegs[XAXIPCIE_AXIBAR2PCIBAR_2L_OFFSET / sizeof(u32)]
			= BarAddr.LowerAddr;

	PcieWriteDmaRegs[XAXICDMA_CR_OFFSET / sizeof(u32)] = XAXICDMA_CR_RESET_MASK;
	PcieWriteDmaRegs[XAXICDMA_CR_OFFSET / sizeof(u32)]
			= XAXICDMA_XR_IRQ_IOC_MASK | XAXICDMA_XR_IRQ_ERROR_MASK;

	PcieWriteDmaRegs[XAXICDMA_SRCADDR_OFFSET / sizeof(u32)] = SrcAddr;

	PcieWriteDmaRegs[XAXICDMA_DSTADDR_OFFSET / sizeof(u32)] = DstAddr;

	PcieWriteDmaRegs[XAXICDMA_BTT_OFFSET / sizeof(u32)] = BytesToTransfer;

Hopefully you can reproduce the issue and fix it in the next version.

Best regards,

Bernhard