DMA reference design in VHDL?

massi_jam · ‎12-12-2008

Hi everyone, I'm trying to implement bus master DMA in my design. I found XAPP1052 but it only provides the example design in verilog. Is there something similar written in VHDL? Thanks in advance.

pwie42 · ‎02-25-2009

hello,

i am currently working on a DMA Ctrl implemented in VHDL and it is allmost ready!

when it is done i gonna release it in some way, and let the forum know!

cherrio,

paul

mcmurtre · ‎07-17-2009

Paul,

I was excited to see your post, as I have a decent PCIe design in VHDL. This week I downloaded and got the Bus Master DMA design working with their Windows demo. My next step is to integrate my design with the bus master design. This would be a lot easier if I had teh bus master design in VHDL. I would be very interested to get your VHDL DMMA Ctrl if you have it ready. Thanks,

Brian

pwie42 · ‎02-25-2009

Hey brain,

jpe, its ready and working, but not released (yet)!

the thing is I am not quit shure hwo to release it, in terms of license, but probably under GPL on opencores.org. I hope this is not a problem for you.

But i have to check first how i gonna release the files i adopted form the coregen PIO design, testcases, and so on... i order not to violate the Xilinx rights on their property!

Basicly the design is the BMD rewritten in vhdl, with working MSI and INTx interrupts, a FIFO backend for the RX and TX engines and a working linux driver for DMA.

Able to achive a bandwidth of160 MB/s Tx and 140 MB/s Rx !

greetz paul

mcmurtre · ‎07-17-2009

Paul,

That sounds great. Good luck working out the details. I just created an account on opencores.org. Just this morning I was looking at Verilog to VHDL translators, although I expect the automated tools aren't a perfect solution. If you already have a working version of the BMD in VHDL that sounds great. Actually I would also be interested in using your Linux driver, as I planned to write one. Good luck getting the details worked out on the core with Xilinx!!

I'll keep watching for release information. thanks again,

Brian

mit_brooks · ‎01-29-2008

Hey Paul,

How did you get on with releasing the BMD in VHDL? I had a look on opencores but couldn't find it there...

I'm just starting to look into a design using PCIe and DMA to stream data. As VHDL is my Harware language, its taking quite a long time and head aches to get around the Verilog!

Tim