05-28-2009 05:03 AM
06-03-2009 04:18 AM
i am currently working on a DMA Ctrl implemented in VHDL and it is allmost ready!
when it is done i gonna release it in some way, and let the forum know!
07-17-2009 12:44 PM
I was excited to see your post, as I have a decent PCIe design in VHDL. This week I downloaded and got the Bus Master DMA design working with their Windows demo. My next step is to integrate my design with the bus master design. This would be a lot easier if I had teh bus master design in VHDL. I would be very interested to get your VHDL DMMA Ctrl if you have it ready. Thanks,
07-28-2009 07:35 AM
jpe, its ready and working, but not released (yet)!
the thing is I am not quit shure hwo to release it, in terms of license, but probably under GPL on opencores.org. I hope this is not a problem for you.
But i have to check first how i gonna release the files i adopted form the coregen PIO design, testcases, and so on... i order not to violate the Xilinx rights on their property!
Basicly the design is the BMD rewritten in vhdl, with working MSI and INTx interrupts, a FIFO backend for the RX and TX engines and a working linux driver for DMA.
Able to achive a bandwidth of160 MB/s Tx and 140 MB/s Rx !
08-06-2009 11:00 AM
That sounds great. Good luck working out the details. I just created an account on opencores.org. Just this morning I was looking at Verilog to VHDL translators, although I expect the automated tools aren't a perfect solution. If you already have a working version of the BMD in VHDL that sounds great. Actually I would also be interested in using your Linux driver, as I planned to write one. Good luck getting the details worked out on the core with Xilinx!!
I'll keep watching for release information. thanks again,
12-18-2009 06:48 AM
How did you get on with releasing the BMD in VHDL? I had a look on opencores but couldn't find it there...
I'm just starting to look into a design using PCIe and DMA to stream data. As VHDL is my Harware language, its taking quite a long time and head aches to get around the Verilog!
03-22-2011 08:45 AM
I'm wondering if you can help me with the code of the DMA in VHDL .
I really need it for my project .
Any documents for DMA would be great .
In fact I need this one explained in the XAPP1052.
Please can you send me the code at this adresse : email@example.com
Thank you in advance .