Hello,
I am using the Xapp1052 design, along with the RootPort Model. I modified the sources, I managed to create a constant flow of Memory Write TLPs from the Tx Interface. During the simultation, after a couple TLPs sent, the signal dbg_ur_no_bar_hit pulses High, wich means:
"This signal pulses High for one USERCLK cycle to
indicate that a received read or write request did not
match any configured BAR."
In the User Guide, it is said that this problem is common. I have made sure I enabled the bus master mode. The address chosen was 0x0 for all TLP transactions.
My Questions:
-> What is the cause of this problem? Is this due to a wrong Address?
-> If the address is the issue, why does this event occur ONE time during the simultation?
Does anyone have an idea? Feel free to ask me questions or suggestions.
Best regards.
