01-19-2010 02:26 PM
I have a Virtex-5 LXT PCIe Endpoint design that will be interfacing a PCIe copper cable and there will be a Pericom PI2QX4402 on the other end. My question is can the GTP transceiver be connected directly to the cable or is a re-driver chip needed? From the datasheet, the RocketIO GTP looks like it should be able to transmit and receive directly. Thanks.
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01-25-2010 12:58 PM
I have done this directly with a Virtex LX50T over a X4 PCIe External Cable. The other end uses a One Stop Systems, Inc. redriver board in a PC - which uses the Pericom redriver.
I just completed a X8 design for an LX110T which I hope to begin testing next month.
01-27-2010 05:50 PM
One caution - the first board I designed for this, I got TX and RX reversed. I triple checked my logic and was convinced I had it right. I wound up reworking 5 PCIe X4 cables - I don't recommend it.
If you'd like, contact me via e-mail and I'll send you a page from my schematic with the PCIe connector interface.
02-10-2010 04:16 AM
I also use the same solution for SX95T. I also use One stop Systems redriver board and x8 external cable. I will begin tests next week
One thing that i want to know is spread spectrum clocking, Do I have to worry about it? I have use different clock sources.
02-10-2010 06:15 PM
By spread spectrum clocking, I assume you are refering to the PCIe ref_clk (100MHz). I followed the lead provided on the Xilinx ML555 PCIe eval board and included a IDT ICS874003DG-02LF Jitter Attenuator for the PCIe Ref_clk with the ability to bypass with a pair of zero ohm resistors. I also have a 200MHz oscillator.
We assemble these boards with the Jitter Attenuator (JA) installed, but recently I tested with them bypassed. My board worked the same with the JA installed configured for 100MHz or 250MHz output and the the JA bypassed.
My testing isn't terribly scientific in terms of measuring jitter or looking at the eye diagrams. Our application deals with images that are 256KB each. I use a DMA engine to download single images which are formatted in the FPGA before they are written to memory. My tests consist of writing random images (via DMA) then reading the data back from memory (non-DMA) and comparing to the original image that has been formatted in software. I downloaded, read-back and compared approximately a million of these images with each of the above settings with no errors.
This design is using X4 PCIe over a 3 meter cable with a One Stop Systems, Inc. host adapter.
I should be receiving boards for a new design which uses a similar setup but using X8. I included the JA on this design as well, simply becausewe now have more lanes (and hence more noise), so I felt that this was a safe bet. We can always leave it off in the future if it proves unneccessary.
Another test that I performed - which I recommend - is a loop-back test using the Chipscope Pro Serial I/O Toolkit. I ultimately shorted one end of a cable and performed a loop-back test over the the cable. This excercise will give you some confidence in the interface.
All-in-all, the External Cable seems fairly robust. In our case, it's helpful to have our electronics in a separate box from the PC.
Good luck with your design!
03-06-2012 01:03 PM
I just received a request for the schematic page that I had offered earlier in this thread. As luck would have it, I just completed an article which details the design of a PCI Express External Cable endpoint using a Virtex-5 LXT FPGA. see:
In the article, I include links to the schematic pages from working designs for both X4 and X8 PCIe Over cable.
Though these designs use Virtex-5 FPGAs (LX50T and LX110T respectively), utilizing PCIe 1.1 (Gen 1), I believe the designs will work with Virtex-6 using PCIe 2.x (Gen 2).
I appreciate any and all feedback, comments, corrections so on and will be happy to answer any questions.