Rasit,
By spread spectrum clocking, I assume you are refering to the PCIe ref_clk (100MHz). I followed the lead provided on the Xilinx ML555 PCIe eval board and included a IDT ICS874003DG-02LF Jitter Attenuator for the PCIe Ref_clk with the ability to bypass with a pair of zero ohm resistors. I also have a 200MHz oscillator.
We assemble these boards with the Jitter Attenuator (JA) installed, but recently I tested with them bypassed. My board worked the same with the JA installed configured for 100MHz or 250MHz output and the the JA bypassed.
My testing isn't terribly scientific in terms of measuring jitter or looking at the eye diagrams. Our application deals with images that are 256KB each. I use a DMA engine to download single images which are formatted in the FPGA before they are written to memory. My tests consist of writing random images (via DMA) then reading the data back from memory (non-DMA) and comparing to the original image that has been formatted in software. I downloaded, read-back and compared approximately a million of these images with each of the above settings with no errors.
This design is using X4 PCIe over a 3 meter cable with a One Stop Systems, Inc. host adapter.
I should be receiving boards for a new design which uses a similar setup but using X8. I included the JA on this design as well, simply becausewe now have more lanes (and hence more noise), so I felt that this was a safe bet. We can always leave it off in the future if it proves unneccessary.
Another test that I performed - which I recommend - is a loop-back test using the Chipscope Pro Serial I/O Toolkit. I ultimately shorted one end of a cable and performed a loop-back test over the the cable. This excercise will give you some confidence in the interface.
All-in-all, the External Cable seems fairly robust. In our case, it's helpful to have our electronics in a separate box from the PC.
Good luck with your design!
Kevin Taberski
