03-27-2012 04:21 AM
03-29-2012 02:13 AM
I had used the "routed.bit" . It faild , too.
X86: SandyBridge, CPU:2520. PCIE-SLOT: 16X, derectly drived by SandyBridge,
Today, when I use insulator to paste on the PCIE finger lane4~lane7, it link success, both gen1xlane4 and gen2xlane4.
03-29-2012 03:39 PM
In addition to what luisb suggested, check http://www.xilinx.com/support/answers/42368.htm to debug the issue further.
This AR is for V5 but the principle applies to V6 as well. Also, try by taping off the lanes as described in the AR below:
03-30-2012 01:57 AM
When I checked http://www.xilinx.com/support/answers/42368.htm to debug the issue, I found that , the RCV_TERM_VTTRX=FALSE.
Anothor, I found that ML605 has sent ST2, but it didn't receive ST2, and it still receive ST1