PCI Express

[chenfang-neusoft]

Hi,

I am new to PCIE endpoint . I use ML605, X86 is ICE200 and intel-3000.

I do follow the document ml605_PCIe_Gen1_x8_pdf_xtp044_13.1_c.pdf. But the PCIE device did not be recognized when using ICE200, while could being recognized when using intel-3000.

When training fail, I found that the ltssm_state changed like 0, 2, 4, 5, 2d, 0, 2, 4, 5 , 2d, 0, 2, 4 , 5,... and stoped at 5.    It means that the TS2 seq did not be received. Why ?

Please give me help. Thanks!

Best wishes!

[luisb]

Did you try the Bitfile that comes with the design files?
You should be able to find it here:
http://www.xilinx.com/support/documentation/ml605_13-4_rd.htm

[chenfang-neusoft]

Thank you!

I had used the "routed.bit" . It faild , too.

ADD:

     X86: SandyBridge, CPU:2520. PCIE-SLOT: 16X, derectly drived by SandyBridge,

Today, when I use insulator to paste on the PCIE finger lane4~lane7, it link success, both gen1xlane4 and gen2xlane4.

[luisb]

Are you using the x4 design or the x8 design?

If you're using the x4 design, then you could be running into this known issue:

http://www.xilinx.com/support/answers/36545.htm

[deepeshm]

In addition to what luisb suggested, check http://www.xilinx.com/support/answers/42368.htm to debug the issue further. 

This AR is for V5 but the principle applies to V6 as well. Also, try by taping off the lanes as described in the AR below:

http://www.xilinx.com/support/answers/38988.htm

Thanks,

DMS

[chenfang-neusoft]

dmsxilinx, Thanks!

   When I checked http://www.xilinx.com/support/answers/42368.htm to debug the issue, I found that , the RCV_TERM_VTTRX=FALSE.

Anothor, I found that ML605 has sent ST2, but it didn't receive ST2, and it still receive ST1