05-15-2012 05:21 AM - edited 05-15-2012 05:29 AM
I have a question related to comunnication between multiple FPGAs using PCIe and Microblaze.
In a nutshell , I have a system with 3 Xilinx V6 FPGAs connected using a PCIe switch. I need to establish a communication between them using this PCIe switch. One FPGA will be running a Microblaze + PCIe core + PLBv46-PCIe bridge and the others will be running VHDL designs + PCIe core. This Microblaze will be used instead of a host GPP system.
Now i know that the communication between two FPGAs in a host GPP system using PCIe can be done by creating PCIe packet with corresponding "destination ID" . However, in this case, since I am using Microblaze instead of a Host GPP, , how does it work ? For instance , in a host GPP sytem,The host will be in charge of enumerating (giving addresses) to each of the PCIe nodes . The host will traverse through available buses and nodes and read their device ID. If the host see a valid device ID, then it will assign an address range for that device. The endpoint will look at this Configuration Write Type 0 from the host and it will decode the "completer ID" address field and it will know what address it's assigned to. .
However, how does this work on a Microblaze system ? Is this process of assigning address spaces for different PCIe end point devices same even in this case ? i.e. how does one communicate between , A->Band A->C, where A is the FPGA with Microblaze + PCIe core + PLBv46-PCIe bride .. How do i know the destination address of other FPGAs connected to the PCIe switche?. Could some one give me some insight on this and give me some pointers ? ?