02-24-2012 09:32 AM
I insert the board into the pcie slot, and there is PCI standard RAM controller in device manager. Once I program the bit file of xapp1052(DMA) into the FPGA, then the board disappears. The bit file is created fellowing steps of the user guide of xapp1052.
who can help me?
thanks in advance~
02-24-2012 12:48 PM
If you re-program the FPGA after the system is running, you need to re-boot the system
in order for the board to be enumerated. The only exception would be in a hot-pluggable
system, which does not include most desktop style PC's.
If you just want to see if the board exists (but not actually use it) after programming, you can
use a utility like PCItree (Google for it - you can download it free) to scan the PCI bus, but
you would still need to reboot before you could access the board using the BAR's.
02-24-2012 08:27 PM
Thanks. But after I reboot the system, I can't find the board in device manager. When I generate the core, I select the device Virtex-6 xc6vlx240t ff1156 -3, and the core is x8 lanes gen2. Because the user guide of the core says the core doesn't support x8 gen2 when speed grade is -1. I don't know whether the core supports DMA transfer when the lane is x8 and speed is gen2, while the speed grade is -1.
02-25-2012 09:31 AM
Now I select the version 1.3 instead of version 1.7 core, the system can detect the board, but the read bandwidth is 700MB/s and write bandwidth is 1.8GMB/s, the system mainboard is x58, I think it's the clock problem, because the synthesize report says timing constraint is not met. but I don't how to solve the problem.
02-25-2012 12:50 PM
Failing timing usually results in a design that just doesn't work, rather than a design
that works at a lower bandwidth. So it looks like this is a system level issue. Some possibilities:
The board is not advertizing the capability of running at PCIe Gen 2 speed and links up at Gen 1 (2.5 Gb)
The system memory interface is slower than the PCIe bandwidth, so even though the board is
connected at 5 Gb you only see 1.8 GB/s write.
In any case, read bandwidth is expected to be lower because it depends on the latency between
issuing the command and receiving the returned data. You can bring up the read bandwidth by
allowing multiple open transactions, but I don't think the demo code uses this feature.
04-04-2012 03:34 AM
I am also facing this issue. I am new to PCIe.
When I follow xtp044, and create the PCIe core, ML605 is detected. But when I follow xapp1052, ML605 is not detected.
I used v1.7 core, and ISE 13.2. There were no errors in synthesis/routing. I configured the link for x8, gen1.
Is it the problem with sub-class: in the former case it was 00, and in the latter 80.
Then I tried v1.3 core. Here I get the error during placement:
ERROR:PhysDesignRules:2399 - The GTXE1 comp core/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD.GTX has POWER_SAVE set to an unsupported value and must be set to 1. Please see Answer Record 39430 for more information.
Should I go ahead and try the hack. But going by this user's experience, it seems to be a terrible hack:
Can someone please help me on this.
04-04-2012 04:12 PM
If your design doesn't meet timing, it could cause the issue you're seeing because the link probably never link trains properly. It could also cause the PC to hang during boot.
Regarding your POWER_SAVE bit issue, I posted it on your other forum post. But basically you need to change your GTX instantiation in the GTX wrapper, so that the fourth bit of this power_save parameter is set to 1.
04-11-2012 01:33 AM
I used v1.3, and performed the simple 1-bit edit. Now I am able to see the device in the PC device manager!
I am using x8, gen1.
But v1.7 is not working with ISE 13.2. Is it a known issue.
Is it fixed for ISE 13.4.
How is v1.7 better than v1.3.
thanks and regards,