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PCIe BMD simulation problem with SP605
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01-23-2012 08:42 AM
Hi,
I am trying to simulate PCIe BMD for SP605 with ISim 13.2. I got a problem that PIO operation doesn't happen once Bus Master bit set. Here is my tests.vhd:
elsif (test_selector = String'("bmd_write_test")) then
writeNowToScreen(String'("Running bmd_write_test"));
PROC_SYSTEM_INITIALIZATION(trn_reset_n, trn_lnk_up_n);
PROC_BAR_INIT (tx_rx_read_data_valid, rx_tx_read_data_valid, rx_tx_read_data, trn_td_c,
trn_tsof_n, trn_teof_n, trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
PROC_TX_CLK_EAT(300, trn_clk);
-- Set the DMA(2) and Interrupt(10) bit in cfg_command
write (Lglobal, String'(" Writing cfg_command REG "));
--hwrite(Lglobal, std_logic_vector(to_unsigned(i, 4)));
writeline (output, Lglobal);
PROC_TX_TYPE0_CONFIGURATION_WRITE (
X"06", x"004", x"00000404", X"F",
trn_td_c, trn_tsof_n, trn_teof_n , trn_trem_n_c, trn_tsrc_rdy_n,
trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
PROC_TX_CLK_EAT(5000, trn_clk);
-- Assert Initiator Reset
write (Lglobal, String'(" Writing DCR1 With 0x01 "));
--hwrite(Lglobal, std_logic_vector(to_unsigned(i, 4)));
writeline (output, Lglobal);
DATA_STORE(0) := X"01";
DATA_STORE(1) := X"00";
DATA_STORE(2) := X"00";
DATA_STORE(3) := X"00";
PROC_TX_MEMORY_WRITE_32 (
X"07", "000", "0000000001", BAR(0)(31 downto 0), X"0", X"F",'0',
trn_td_c, trn_tsof_n, trn_teof_n , trn_trem_n_c, trn_tsrc_rdy_n, trn_terrfwd_n,
trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
PROC_TX_CLK_EAT(100, trn_clk);
......(other BMD register operation)
-- Write DMA Start
write (Lglobal, String'(" Writing DCR2 With 0x01 "));
--hwrite(Lglobal, std_logic_vector(to_unsigned(i, 4)));
writeline (output, Lglobal);
DATA_STORE(0) := X"01";
DATA_STORE(1) := X"00";
DATA_STORE(2) := X"00";
DATA_STORE(3) := X"00";
addr := std_logic_vector(unsigned(BAR(0)(31 downto 0)) + X"04");
PROC_TX_MEMORY_WRITE_32 (
X"0d", "000", "0000000001", addr, X"0", X"F",'0',
trn_td_c, trn_tsof_n, trn_teof_n , trn_trem_n_c, trn_tsrc_rdy_n, trn_terrfwd_n,
trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
PROC_TX_CLK_EAT(100, trn_clk);
From ISim only first two PIO operations happened. rest of them didn't happen. Once I move cfg_command writing operation down to bottom after BMD config operation, it seems I can see all BMD config operations. but another problem happened that is the second DMA will not happen becuase any PIO operation after first DMA will not happen. What am I missing here?
Thanks,
Jeff
Re: PCIe BMD simulation problem with SP605
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01-24-2012 03:48 AM
Can you also upload ISIM's transcript?
Re: PCIe BMD simulation problem with SP605
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01-24-2012 07:43 AM
thanks for your reply. here is message from ISim Console:
ISim>
# restart
ISim>
# run all
Simulator is doing circuit initialization process.
at 0 fs: Note: [0 fs] : System Reset Asserted... (/board/).
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL
[ 0 ns ] : CoreName = s6_pcie_v1_4
[ 0 ns ] : Running bmd_write_test
Finished circuit initialization process.
at 3996 ns(3): Note: [3996000000 fs] : System Reset De-asserted... (/board/).
[ 40324.246 ns ] : Transaction Reset is De-asserted
[ 114400.246 ns ] : Transaction Link is Up
[ 114400.246 ns ] : PCI EXPRESS BAR MEMORY/IO MAPPING PROCESS BEGUN..
BAR 0 = 0x10000000 RANGE = 0xFFFFFC00 MEM32 MAPPED
BAR 1 = 0x00000000 RANGE = 0x00000000 DISABLED
BAR 2 = 0x00000000 RANGE = 0x00000000 DISABLED
BAR 3 = 0x00000000 RANGE = 0x00000000 DISABLED
BAR 4 = 0x00000000 RANGE = 0x00000000 DISABLED
BAR 5 = 0x00000000 RANGE = 0x00000000 DISABLED
BAR 6 = 0x00000000 RANGE = 0x00000000 DISABLED
[ 114400.246 ns ] : Setting Core Configuration Space...
[ 114412.146 ns ] : PROC_PARSE_FRAME on Transmit
[ 114824.146 ns ] : PROC_PARSE_FRAME on Transmit
[ 115236.146 ns ] : PROC_PARSE_FRAME on Transmit
[ 115648.146 ns ] : PROC_PARSE_FRAME on Transmit
[ 116060.146 ns ] : PROC_PARSE_FRAME on Transmit
[ 116472.146 ns ] : PROC_PARSE_FRAME on Transmit
[ 116884.146 ns ] : PROC_PARSE_FRAME on Transmit
[ 117296.146 ns ] : PROC_PARSE_FRAME on Transmit
[ 117708.146 ns ] : PROC_PARSE_FRAME on Transmit
[ 117788.146 ns ] : PROC_PARSE_FRAME on Receive
[ 118236.146 ns ] : PROC_PARSE_FRAME on Receive
[ 118716.146 ns ] : PROC_PARSE_FRAME on Receive
[ 119132.146 ns ] : PROC_PARSE_FRAME on Receive
[ 119612.146 ns ] : PROC_PARSE_FRAME on Receive
[ 120028.146 ns ] : PROC_PARSE_FRAME on Receive
[ 120476.146 ns ] : PROC_PARSE_FRAME on Receive
[ 120924.146 ns ] : PROC_PARSE_FRAME on Receive
[ 121372.146 ns ] : PROC_PARSE_FRAME on Receive
Writing cfg_command REG
[ 122920.146 ns ] : PROC_PARSE_FRAME on Transmit
Writing DCR1 With 0x01
[ 124132.146 ns ] : PROC_PARSE_FRAME on Transmit
Writing DCR1 With 0x00
[ 124544.146 ns ] : PROC_PARSE_FRAME on Transmit
Writing WDMATLPA With 0x00
[ 124956.146 ns ] : PROC_PARSE_FRAME on Transmit
Writing WDMATLPS With 0x00
[ 125368.146 ns ] : PROC_PARSE_FRAME on Transmit
Writing WDMATLPC With 0x00
[ 125780.146 ns ] : PROC_PARSE_FRAME on Transmit
Writing WDMATLPP With 0xFEEDBEEF
[ 126192.146 ns ] : PROC_PARSE_FRAME on Transmit
Writing DCR2 With 0x01
[ 126604.146 ns ] : PROC_PARSE_FRAME on Transmit
[ 130460.146 ns ] : PROC_PARSE_FRAME on Receive
Stopped at time : 171596104 ps : File "v:/hipsBuilds/O_hips_v19.0/rst/hips/gtpa1_dual/GT
ISim>
there is no error during simulation. but the DMA did not happen.











