PCI Express

[technicolor]

Hi John,

Thanks for the help.

With your we could identify that the Xilinx core is ok and that the processor seems to be the problem

Rgds,

Technicolor

[maquicoser]

Agree: there is a case statement looking at the format and type of the packet. I think it should work fine, but maybe there is a mistake in the message portion of the case statement. Take a look and see if the paramter identifying the message is correct

[mwalden]

Hi,

I want to simulation Legacy Interrupts with a Virtex-7 PCIe Endpoint. I got the same problem, that the Message is not in the rx.dat, nor the RP RC interface nor the cfg_msg:* interface.

I found a parameter called AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000

Do I have to modify this parameter? Which value? Whats about the parameter         AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"?

Best regards,

Michael