01-26-2012 05:29 AM - edited 01-26-2012 05:30 AM
Thanks for the help.
With your we could identify that the Xilinx core is ok and that the processor seems to be the problem
04-01-2012 04:13 AM
Agree: there is a case statement looking at the format and type of the packet. I think it should work fine, but maybe there is a mistake in the message portion of the case statement. Take a look and see if the paramter identifying the message is correct
12-21-2012 02:30 AM
I want to simulation Legacy Interrupts with a Virtex-7 PCIe Endpoint. I got the same problem, that the Message is not in the rx.dat, nor the RP RC interface nor the cfg_msg:* interface.
I found a parameter called AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000
Do I have to modify this parameter? Which value? Whats about the parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"?