PCI Express

[k-50]

Hello! I'm new in PCIe development.

I have a problem with PCIe link training on my Spartan6 (xc6slx25t-3fgg484) FPGA. I can't understand why.

To be sure that there is no configuration time issue I power on CPU when FPGA already configured, also I have include chipscope to observ GTP outputs.

I attach schipscope screenshots.

Any idea what's problem?

[deepeshshakya]

Hi,

If you haven't already checked, please have a look at the document linked in the following answer record:

http://www.xilinx.com/support/answers/42368.htm

This document was written for V5 but the principle applies to S6 too.

-DMS

[k-50]

Thank you! Very useful doc.

In my case LTSSM in detect mode.

What data should I see on TX and RX ports in this state?

[deepeshm]

Do you mean ltssm state signal indicates you are in detect state? It never progresses beyond the detect state?

If so, please check page 15 of the doc. Do you see the sequence of steps described happening in your design.

[jayer]

Also, i notice there is alot of activity on your RXSTATUS outputs. Normally this will be 000 except during the detect state or if the link is in electrical idle. Its hard to tell from the screen shots but I suspect its probably incating some errors. You can check the S6 GTP UG for the encodings.

-John

[k-50]

Hello.

When gtp_reset_done changes to 1, PHYSTATUS changes to 0. And it is in 0 all time. This means that RX not detected.

LTSSM always in detect mode (or it goes from detect to initial state and again to detect).

pipe_gt_tx_elec_idle = 1. rx_enter_elecidle = 0.

RXSTATUS changes from 3'b100 to 3'b111 and then to 3'b000.

There is a lot of data in RX port. 

Also I see data on TX port by oscilloscope.