PCIe root complex implementation

ivanwong · ‎12-15-2011

I would like to implement the PCIe Root Complex. My plan is to start with the CoreGen IP (from ISE13.3) and port to ML605.

But, my question is how to verify the design in hardware?

Can i test with just ML605 as root complex and ML507 as endpoint, using SMA cables to connect them, to test with a single DW transfer between them?

Also, if we want to test with the PCIe interface (not through SMA cable), is there any existing hardware board we can buy so that we can plug both ML605 and ML507 card on the board (something like motherboard) and test?

Thanks,

Ivan

barco2 · ‎02-13-2009

LeCroy offers a product called "PCI express DVT platform PXP-100a" which is from the former Catalyst company. I use it here for connecting the ML605 as root port to other PCIe cards. Basically this platform is a crosswired two-slot backplane with clock generator, reset logic and power-supply.

Regards

Martin

luisb · ‎04-06-2010

The FMC card below should work for you as well.

http://hitechglobal.com/FMCModules/FMC_PCIExpress.htm

stancao · ‎03-13-2012

Hi,luisb:

I would like to implement the PCIe Root Complex on ML605,too.

I'm going to buy the fmc card that you recommended above.

But how should I connect the xilinx pcie block ip to the HPC connector?

Especially, how should I deal with the GTX stuff? Do I have to modified the physical layer of the xilinx pcie ip?

Thanks a lot!

luisb · ‎04-06-2010

All you have to do is change the UCF with the correct location constraints. I have a UCF that should work. I'm on my cell phone right now, so I'll post the locations when I'm In the office tomorrow. If I don't, send me a message to remind me.