PCI Express

[arun_ajs]

Hi

I'm using a system for transferring data between host PC and ML605.

I used the mhs provided in  AR #43371 as a base.

I added two extra PCI BARS, so as to access the axi_cdma and axi_pcie registers.

I am able to access the DDR3 RAM mapped by PCI BAR0 successfully.

But I can't access the axi_cdma and axi_pcie cores' registers mapped with PCI BAR1 and BAR2. All reads are givceing 0xffffffff.

Is it because the registers are on axilite not axi4? How can I access these from PC? 

I plan to  control the simple DMA transfer by giving DMA buffer address to AXIBAR2PCIBAR register on axi_pcie and setting other registers on axi_cdma directly from host. Is this the right procedure. Please let  me know if there's a better way.

P.S: Why does the AR# 43371 design have a axi2axi connector?

Regards

Arun

[arun_ajs]

I connected the Control interface of both axi_pcie and axi_cdma to axi4 (earlier these were connected to axilite) and made axi_pcie the master. Still I cant access the registers from host PC through the PCI BARS. The reads return FFFFFFFF, not the default values or the patterns i write to them.

[luisb]

Will you add your new MHS? I'd like to take a look at you new system.

[arun_ajs]

Changes made to the base design:

 1.Removed  CDMA_1
 2.Remove SG support of CDMA_0
 3. Made SDRAM Address space 512 MB
 4. Made PCI x4 from x1

 5. Added CDMA Interrupt to Interrupt Controller

 6. Connected S_AXI_LITE  of axi_cdma to axi4 with axi_pcie.M_AXI as master

 7. Connected S_AXI_CTL  of axi_pcie to axi4 with axi_pcie.M_AXI as master

 8. Added two additional BARS for accessing S_AXI_LITE and S_AXI_CTL registers.

 9. Increased aperture of BAR 0 to 128 MB

[arun_ajs]

Hi

I have shifted to a system, where I use the microblaze code to trigger the DMA.

A part of the SDRAM is shared by the microblaze and the host through the PCIe BARs.

I got my system to work, both PIO and DMA. But I noticed a peculiar issue.I'm reporting it here.

I have used C_INCLUDE_BAROFFSET_REG = 1. 

I'm programming the AXIBAR2PCIBAR0 Register and reading it back. It reads back the written value.

However, it doesn't affect the address translation. The address translation always happens to the PCIe address 0x00080000.

So the DMA always happens to this address, irrespective of what I write to AXIBAR2PCIBAR0.

Fortunately, the first page returned by the Linux kernel using kmalloc with GFP_DMA flag (Low Memory DMA) is at address 0x00080000. So the DMA is made possible. Other addresses at either high memory or returned by further calls to kmalloc, doesnt work.

[jdekoker]

Hi arun_ajs

I observe almost the same behavior as yours:

I program the AXIBAR2PCIBAR0 (and read it back to confirm that my value is well written)

And my translation seems to not working because I always find my datas in 0x0000_0000

Question: Do you solve this problem ?

Thanks in advance

[hse07013]

@jdekoker:

Which value do you write into the AXIBAR2PCIBAR0 register? And which size has the PCIe C_AXIBAR0 address range?

The AXIBAR2PCIBAR0 value must be greater equal to C_AXIBAR0 address size.

Best regards,

Bernhard

[jdekoker]

Hi hse07013

Where did you find this contraint "The AXIBAR2PCIBAR0 value must be greater equal to C_AXIBAR0 address size." ?

Because I'm no very sur about it.

Today I concluded that my translation doesn't work on my IP PCIe_AXI on a ML605.

But if I increase  C_AXIBAR0 address size and if I do myself the translation, then I can write my data in the right address of my host. My method as only 1 disavantage : I waste AXI addresses

Thanks for your concerning

[hse07013]

Sorry, i was unclear with my description.

The width of C_AXIBAR0 minus one can be considered as zeros in the lower AXIBAR2PCIBAR0.

For example, the C_AXIBAR0 is 4 kiB = 12 bits.

Only the upper 21 bits of AXIBAR2PCIBAR0 are active.

The following code example assumes a 32 bit only system and size of C_AXIBAR0 equates to 4 kiB:

size_t hostAddress = 0x0123456789ABCDE0; // any host address

size_t data = 0x1111222233334444; // any data

// The address window for AXIBAR2PCIBAR0

const size_t alignedAddress = hostAddress & ~(4 * 1024 - 1);

// The address offset of alignedAddress

const size_t alignedOffset = hostAddress & (4 * 1024 - 1);

Xil_Out32(AXIBAR2PCIBAR0_ADDR, alignedAddress);

Xil_Out32(C_AXIBAR0_ADDR + alignedOffset, data);

Now 0x1111222233334444 is transferred to the host memory at 0x0123456789ABCDE0!