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Visitor
sm1109
Posts: 8
Registered: ‎02-04-2009
0

Problems in simulation (Top level file for PIO design)

Hi all,

I am using ModelSim to simulate the PIO design. I made a new project in ISe and chose the default simulator as ModelSim. I added all.v files to this project and did a Behavioral Simulation. The ModelSim window opened up and after adding all signals to waveform, I could not see any of the TRN interface signals. Instead, the clk_generator verilog file is coming up as the top level file and the signals in the waveform are some clock related signals. I want to be able to see the TRN interface signals. But I cannot see them in the simulation.

Can someone explain how they simulated this design. I am kind of new to this core and ModelSim.

 

Let me know.

Thanks. 

Xilinx Employee
kylocke18
Posts: 70
Registered: ‎08-01-2007
0

Re: Problems in simulation (Top level file for PIO design)

Hello,

 

I'm assuming you're using the PCIe Block Plus core for this:

 

First thing's first, make sure the endpoint (EP) files are set up correctly.  This is described for the Block Plus core in the Getting Started Guide (GSG343), page 21.  Set the "xilinx_pci_exp_ep" file as the top level if this is not done automatically.

 

Now for the PIO simulation.  The easiest way is to just open ModelSim separately and then run the "simulate_mti.do" file located in the "<core_name>\simulation\functional" folder. 

 

But if you do want to do it all through the ISE GUI, you will need to take a look at the "board_rtl_x04.f" and "xilinx_pci_exp_cor_ep.f" files and make sure you add all Verilog files listed there into your project.  Note that in the "board_rtl_x04.f" file, it performs a +incdir+ operation for the "tests" folder and the "dsport" folder.  So for your ISE project, you will need to add the source files from those folders as well (unless they are otherwise listed in the .f files and you already added them).

 

Then when you go over to the "Behavioral" tab in ISE, the "board.v" file should be the top-level listed for simulation.  You would highlight that file in the "sources" window then in the "Processes" window run the "Simulate Behavioral Model" option there.  This should run the default simulation called "sample_smoke_test0," which is located in the "sample_tests1.v" file.

 

-Kyle

Visitor
sm1109
Posts: 8
Registered: ‎02-04-2009
0

Re: Problems in simulation (Top level file for PIO design)

Hi Kyle,

So I could see the signals in the waveform. But all the signals are Z ie there is no stimuli or any output. I thought I would be able to see trasactions taking place. Is there something else I should be checking?

 

Thanks for your help. 

Xilinx Employee
kylocke18
Posts: 70
Registered: ‎08-01-2007
0

Re: Problems in simulation (Top level file for PIO design)

Hello,


Can you attach or copy-and-paste your ModelSim transcript output?

 

Thanks,
Kyle

Visitor
sm1109
Posts: 8
Registered: ‎02-04-2009
0

Re: Problems in simulation (Top level file for PIO design)

Hi Kyle,

Attached the transcript.

 

 

Xilinx Employee
kylocke18
Posts: 70
Registered: ‎08-01-2007
0

Re: Problems in simulation (Top level file for PIO design)

Hi,

 

This is a tough one to figure out.  One thing I notice in your transcript is this line:

 

" # do {xilinx_pci_exp_ep.fdo}"

 

If you had run the simulation on the board.v file as I described previously, that line should say something like "do {board.fdo}".

 

I would also recommend at this point that you try running the "simulate_mti.do" file generated with the core, outside of ISE (I referred to this in an earlier post).  Assuming all your libraries are set up correctly, the simulation should run "out-of-the-box", and if it does not that may tell us something about this issue.

 

-Kyle

 

 

Visitor
sm1109
Posts: 8
Registered: ‎02-04-2009
0

Re: Problems in simulation (Top level file for PIO design)

Thanks. I guess I wasnt simulating the board.do but was simulating the xilinx_pci_exp_ep.v. But after simulating the board.v file, I get a lot of warnings as attached in the transcript. I am not sure this time what is going wrong.

I will try with the simulate_mti.do

 

Thanks so much. 

Xilinx Employee
kylocke18
Posts: 70
Registered: ‎08-01-2007
0

Re: Problems in simulation (Top level file for PIO design)

Hi,

 

I'm not concerned with most of the warnings--they are expected.  However, this one is an issue:

 

  ** Warning: (vsim-PLI-3003) :/Xilinx/10.1/ISE/verilog/mti_se/unisims_ver/unisims_ver_SmartWrapper_source.v(15931): [TOFD] - System task or function '$lm_model' is not defined.

 

# Region: /board/xilinx_pci_exp_4_lane_downstream_port/xilinx_pci_exp_4_lane_dsport/pci_exp_4_lane_64b_dsport/plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST/gt11_swift_1/I1

 

 

This warning indicates that your SmartModels are not set up correctly.  Make sure you carefully check all the items listed in this AR:

http://www.xilinx.com/support/answers/24800.htm

 

-Kyle

Visitor
sm1109
Posts: 8
Registered: ‎02-04-2009
0

Re: Problems in simulation (Top level file for PIO design)

Hi Kyle, 

I followed the AR but I am not sure about the Environment variable.

In my system the  Variable LMC_HOME points to: C:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt

I dont think this is correct. Now I changed it to: C:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt\lib\pcnt.lib . Still I did not notice any difference in the simulation. Am I missing something else here?  

 

Thanks. 

Xilinx Employee
kylocke18
Posts: 70
Registered: ‎08-01-2007
0

Re: Problems in simulation (Top level file for PIO design)

Hi,

 

This first thing you listed for LMC_HOME is correct ( C:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt ), just make sure that is the correct ISE 10.1 install path that you have.

 

Assuming you have carefully checked your modelsim.ini file according to AR 24800, the issue may be that ModelSim is picking up some other modelsim.ini file somewhere else.  So be sure you copy the modelsim.ini file you have checked according to AR 24800 into the ModelSim install directory (for example, "C:\modeltech_6.4a"), and the C:\Xilinx\10.1\ISE directory for good measure.  And if you have another modelsim.ini file in your ISE project directory, take it out.

 

-Kyle