PCI Express

[lordgalloth]

Hi all,

we have problems that PCI Express endpoint do not meet its timing in our designs. If it is only the endpoint everything is OK, but

when other component is added (like DMA drivers, etc.), design fails to meet the timing and all critical; paths are in PCI Endpoint. 

To make sure that our part of design is not competing for resources, we constrained it to the other half of the chip than endpoint, but it

still did not work. Therefore I think that only possible solution is to create constrains for the endpoint itself, so it will place& route correctly.

Unfortunetelly it is really hard to orient with the flat design of the endpoint, therefore I would like to restore hierarchy of the netlist

generated from coregen.

Is there any possible way how to do it? Or do you have any other advice how to force endpoint to always meet the timing? 

Thank you for any help or hint.

Jan

[deepeshm]

Hi,

1. Which device are you using?

2. If you generate the core and implement the example design, does it meeting timing?

3. In MAP and PAR, do you have -xe set to 'c'?

4. If you have '3' set, try different seed option in MAP. It is '-t' option. For more information on this

    have a look at 'Development System Reference Guide'. There is a seperate chapter on MAP.

Thanks,

DMS

[lordgalloth]

---

dmsxilinx wrote:

Hi,

1. Which device are you using?

2. If you generate the core and implement the example design, does it meeting timing?

3. In MAP and PAR, do you have -xe set to 'c'?

4. If you have '3' set, try different seed option in MAP. It is '-t' option. For more information on this

    have a look at 'Development System Reference Guide'. There is a seperate chapter on MAP.

Thanks,

DMS

---

Hello DMS,

thanks for your fast answer.

1) I am using xc5vlx110t and it is possible for us to use also 155t, but timing failed for both chips.

2) Yes, example design met timing, but only when it was synthesised, mapped and placed by ISE11.2 (I test both 10.1 and 11.2)

3) Yes I have a set these parameters. In fact I tested all strategies defined in PlanAhead plus several of my own.

4) I did not tested change of the seed,it's my mistake :-( I will go through the manual yet again to make sure I did not forget some other thing.

The timing is sometimes met even when we comments parts of our design, but the problem is, when we add all our design, that the PCI Endpoint fails. So I am looking for some way, how to be sure, that PCI Endpoint always meet the timing. No matter of the change in our design. So my idea was to constrain PCIEndpoint to same part of the chip and do not allow the usage of this part of chip by any other component. But still the other components are able to produce timing error in PCI_endpoint, which represents problem for our team. Therefore I am trying to look for approach that will force the PCI Endpoint to place and route correctly.

I already tried to use guided map ( I commented the parts of our design, met timing and this was a guide for a whole design), but It still did not meet timing in the endpoint (in fact the whole timing score was much worse)

As a second thing I created LOC constraints from the par run which met the timing (part of the design was commented) and tried to call map on it, but there the timing was worse or map failed because of the impossible constraints.

So now I though of creating the area constraints for the PCI endpoint to force it to meet timing, but the PCI endpoint netlist is flat and therefore it is hart to even orient in it...

As for the -t options I do not see how to use it for our problem, because if I understand it correctly, if there are a change in the design, map will need a new -t parameter. But in our project we need that this part was placed no matter what other part of the design is doing (if there is no resource collision). 

So even if -t will work, the original question still remains, how to ensure, that the endpoint will place after there is a change in our design? Please correct me if I am wrongs, thanks.

Thank for the answer,

Jan

[davesteele]

Dear Jan,

Welcome to the real world. We are using an LX110T-2 with PCIe x8. Sometimes it fits, sometimes it doesn't. Takes an hour to find out. Even an irrelevant change in the user design breaks it. I've had my top man locking down stuff but to little avail. None of this is much use to you. However:

1/. If you use a lot of block ram, try and reduce it. The block ram seems to get badly placed especially in 10.1. (11.1 is better)

2/. Invest in Syplify Premier Pro. Haven't tried it myself, but I'm assured (by Synplify) that it can read encrypted Xilinx cores and resynthesize. We have a high fanout on the rx interface and a simple replicate would help the timing. The Xilinx tools don't seem to do this (Would XST??? Anyone know)

I've had trouble in an Supermicro X7DA8 motherboard (works fine in X6DA8). Anybody got anything to add to this?

[deepeshm]

Hi Jan,

Unfortunately there isn't straight forward solution for that.

You might want to try Partitioning and Smart Guide feature.

I wouldn't say this would help but it would be worth trying.

Creating directed constraints might be another possibility

but it will make the tool inflexible in placing other parts of the

design and hence breaking the timing in other parts of your design.

DMS