PCI Express

[maxascent]

I have a Virtex 5 PCIe design in VHDL and want to check for a memory write 32 TLP received at the root port. In the user guide it says to use the task TSK_EXPECT_MEMWR but this seems to be for verilog. How would I do this in VHDL?

TIA

[yangliiris]

In VHDL You can use

 PROC_TX_MEMORY_WRITE_32

to write to PP and them read back using

 ( PROC_TX_MEMORY_READ_32