Hi all.
I have problem with V7 EP in BusMaster design. FPGA: .xc7vx485t, package: ffg1761, speed: 2.
I have quite simple design in EDK(v14.1):
- axi_interconnect (v1.06.a)
- simple user AXI component - master (output counter on demand), also contain axi slave (config registers for master)
- axi_pcie component (v1.03.a)
- bram, etc (not used in current design, for now)
axi_pcie component config:
- BAR#0 - 64bit, AXI Slave DataWidth 128bit
- PCIE ADDR value (out to PCIE HW IP, 64bit) = 0x1A2B3C4DFE124000
- CMPS = 256byte
transaction info:
write to BAR#0 AXI Slave port 10DW - lead to FPGA TRN PCIE EP Mem64Wr Request with TAG==0 (before this was RP MemWrReq with TAG!=0 -> set up config reg in design via PCIE from RP). I have only one AXI Slave write during test.
Like I can see, I have such PCIE TLP package (incoming port at FPGA design PCIE_2_1 component, please look at attach for TRN control during tx)
0x60000010
0x01a000ff
0x1a2b3c4d
0xfe124000
0x78563412 - payload#0
...
... - payload#9
TLP port of PCIE HW block accept it correctly. TRNFCPH/TRNFCPD first decr (-1) and after some time it incr back (20-1f-20 and 134-130-134 in hex for TRNFCPH/TRNFCPD changes). But I have no activity at RP after this PCIE Mem64Wr request from EP.
PCE RootPort I took from Coregen 7 Series Integrated Block for PCI Express v1.3/v1.4 ( later I checked Virtex-6 Integrated Block for PCI Express v2.5/v1.7 - same behaviour -> no EP PCIE Mem64Wr Request output from RP).
I can see that RP PCIE Mem64Wr/Mem64Rd requests is OK - I can see it at Modelsim waveform and "debugprint" in Modelsim transcript. Even after my EP Mem64Wr request failed I can see that RP PCIE Mem64Rd requests is OK (I have 3 RP PCIE Mem64Rd from testbench after couple of uSec of waiting).
I will be very appreciated for ideas or solutions.
Thanks in advance.
