Hello,
I am using the endpoint block plus (virtex5) to implement a 4x PCIe interface. The hardware that I am using will support an 8x link, however my design is currently only operating at 4x.
One of the GTPs that is connected to two of the unused PCIe upper lanes has a reference clock that I need to use in a neighbouring GTP tile. In order for this clock to be provided to the neighbouring GTP tile, I have to instantiate this GTP in my VHDL such that it can forward the clock (as described in AR33473).
I believe that in doing this, some of the RX circuitry is being enabled and as a consequence causing issues with the PCIe interface. I believe that the root complex is detecting a load on the unused GTP and attempting to train with more than 4 lanes. This seems to be causing the root complex to enter into polling.compliance - which is likely because the unused GTP will not exit from electrical idle and perform any form of training.
Has anybody else ever experienced anything like this?
Can anybody suggest any firmware work arounds?
I can potentially perform hardware modifications to disconnect the unused lanes, but a firmware solution would be preferred.
Thanks in advance.
