07-08-2012 09:47 PM
Can some one help me resolve the following issue.
We have a pcie bit file which gets loaded into system and when we do a restart to get the pcie enumeration the bit file hangs. but the same bit file actually works fine in two other systems.
07-08-2012 10:36 PM
Can you add more information as to what you mean by "the bitfile hangs" during restart, so that others can help you. Do you mean your PC hangs during restart (boot) or the FPGA is not detected or something else?
Also what do you mean by "two other systems"? I assume here is that you mean two other FPGAs/board, and not two other PCs or two other PCIe system (like two different bridges or switches). Can you clarify on this as well?
Can you give us more information on your PCIe setup? Is this PCIe GEN1 or GEN2? How wide is the lane (x1, x4, etc)? What device is this for? What core version? Is this your own / custom design or is this the example design Xilinx provided; Have you tried the example design that comes with the core (PIO design -- generated along with the core and reside in the example design folder within the core directory)?
If they're two different FPGAs or board, are they the exact same board design (termination, routing, etc.) and FPGA type (speed grade, silicon version, etc.)?
First thing I would suggest you to check if you meet timing on the design; pay close attention to any unconstraints clk path if there's any. Double check your constraints and make sure all the constraints that is provided in the example design is in your current .ucf now. You may have variance in PVT that is enough to make it not work.
Also, it would be great if you can do a quick ChipScope captures and figure out which ltssm_state your core is stuck on. In normal operation, this ltssm_state should indicate that you are in state L0 (more information about this signal is in the PCIe core User Guide). Also, add RXstatus signal from the transceivers and check if there's any issue with the link (more information about this signal can be found in the device transceiver User Guide).
07-08-2012 10:53 PM
The PC hangs when i load that particular bit file on same board on PC1 and PC2.
same bit file and same board works fine on PC3 and PC4.
board is a custom board. and we have working PCIe bit file which works on all the PC's.
The bit file for which we have hang issue is having some other functions on top of the pcie bit file.
07-08-2012 10:59 PM
When you add more functions on the bad bitfile, Did you increase the amount of BARs or change the size of the BARs? If so, how big was in the working one and how big was in the non-working ones?
Check with ChipScope for the ltssm_state signal as I suggested in the previous post, that would help us know where it gets stuck.
07-08-2012 11:19 PM
I will look through in chipscope pro.
Thank you for response.
I got to know that extending PERST# signal will solve this kind of issues. want to know if it solves.
07-09-2012 12:16 AM
When you extend the perst signal, you may introduce a new problem where it may miss enumeration altogether; but it may be a good test to do.
From case history, I know a small choice of PC would assert PERST signal multiple times during boot and sometimes cause issue with our transceivers. You may want to check how many times your PC asserts this PERST signal; if it's asserted multiple times during boot, you may want to check if you can implement a logic where it would "filter" this reset (or put caps on the reset line to help filter them out)
07-12-2012 09:21 PM
PERST is usually connected to the system reset of our PCIe core. It's a reset signal coming from the PCIe slot.
The information about this signal should be in the core User Guide and also in the PCI Express specification.