09-01-2009 08:28 AM
Hello, I am using ML507 board to develop the PCIE. I want to know where is PCIE 100MHz clock from?
I know the FPGA diff_clk pins which UCF file constraints is AF3/AF4, which from PCIE connector A13/A14 pins.
So I take it that 100MHz clock is from MotherBoard to PCIE connector A13/A14 pins ，then to FPGA diff_clk pins AF3/AF4 ??
Is it correct??
09-02-2009 09:35 AM
Those are outputs from the FPGA. If the FPGA is not programmed properly, then there will be no clock on those pins.
Look at the design you have, and check it to see what is supposed to be driving those pins.
Download the reference design: (described in this pdf)
And refer to page 18 to check that your board is working properly,
Xilinx San Jose
09-02-2009 09:48 AM
What you said in your first post is correct. The PCIe 100MHz clock comes from the motherboard and sources the A13 and A14 pins of the PCIe connector. From there, on the ML507, this clock goes to the AF3 and AF4 pins on the FPGA, as an input.
It sounds like you are not seeing a clock signal on the PCIe connector. If this is the case, it's possible that the Motherboard (more specifically the Chipset/Root Complex) is turning off this slot if it does not see a viable PCIe link partner present.