In order to discover what the dynamic and static power dissipation will be in a new design with a Xilinx® FPGA device, we provide a power estimation spreadsheet:

 

http://www.xilinx.com/products/design_resources/power_central/index.htm

(XPE Spreadsheets)

 

http://www.xilinx.com/products/design_resources/power_central/ug440.pdf

(the instructions for its use)

 

The dynamic power depends on the rate at which the signals are toggling, or switching. How do you estimate these toggle rates?

After choosing the number of elements, such as CLB’s, BRAM’s and so on, one is asked to estimate the switching rate. A common mistake is to just pick a number, like 50%, and move on.

 

Some Simple Rates

 

First, let us look a 4-bit binary counter. If one averages all the transitions of the four outputs, one discovers that the actual average rate is quite low. The LSB switches on each clock, so it is at 100%. The next most significant bit is half that, or 50%. The next bit is 25%, and the MSB is 12.5%. The average is just that: 100+50+25+12.5 divided by 4, or about 47%.

 

If we continue on to an 8-bit binary counter, we get about 25%. In general, the more states we have, the less the toggle rate. If one has a 10 state one-hot state machine, the toggle rate of the states is no more than 1 in 10, or 10% (only one state may change on any clock).

A full amplitude range sine wave into an eight-bit analog to digital converter may be even less than an eight-bit counter, as the sample values may not even change on each clock cycle, as the sample rate may be many times faster than the sine wave frequency. In such cases, the toggle rate may be 10% or less. Even at the fastest sine wave frequency, the rate for an eight-bit converter will not be more than 25%.

 

An exception that leads to high toggle rates is the result of multiply-accumulate operations on random data, which may approach 50%. The question is, “How random is the data?” Most applications process data from sensors, which are operating well above the noise threshold, and the input data is again well behaved, and toggle rates are much less than 50%. In communications systems, where separating signals from noise is common, high toggle rates will often occur in the multiplier-accumulate blocks, and 50% may actually be a good estimate of the toggle rate.

 

What It All Means

 

When the power estimation spreadsheet is completed, the result is, yes, you guessed it: an estimate! After all, the engineer is still guessing at the toggle rates. The final step is to then simulate the design using the XPower tool:

 

http://www.xilinx.com/products/design_tools/logic_design/verification/xpower.htm

 

Of course, this implies you actually have a test bench, which does more than just check a few clock cycles of your design. Again, to simulate a real signal entering your logic, and being processed, is no small effort, and not doing so leads to a result that is even less useful than that of the estimator spreadsheet.

 

Summary

 

Estimating power in a FPGA device is a non-trivial exercise. There are tools designed to help with the task, but the tools are only as good as the effort made to provide them with accurate information. Poor estimated toggle rates and insufficient simulation test benches are key examples of inputs that might cause the results to be wildly inaccurate.

 

Austin Lesea

Message Edited by austin.lesea on 08-22-2008 05:58 PM