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Happy New Year: Moore, More Moore, and More than Moore
Happy New Year: Moore, More Moore, and More than Moore
We are all now quite familiar with “Moore’s Law.” Gordon Moore, at Intel, in a 1965 paper, predicted the shrinking of dimensions for integrated circuits, and his prediction has now taken on the guise of a physical law.
http://en.wikipedia.org/wiki/Moore%27s_law
And, just as his prediction has been tested in every generation of technology, so have people predicted the end to the shrinking. The “end” has been predicted at various times, and has varied from ending in 2007 (which it didn’t) to “never.”
The truth lies somewhere in between, obviously.
More Moore
The term used to describe “business as usual” is ‘More Moore.’ It means just that, that there will be twice as many transistors on a particular dimension die in the next generation.
Unfortunately, practical limitations have reduced the improvements we have enjoyed since 1965: gone is the 8-10% clock speed improvement with every generation, and no longer is the power per function reduced with every generation. What we see now is a gradual end to the speed and power improvements.
But, engineers can be clever, and even cleverer. In this fashion, we still improve processing speed (perhaps not by increasing clock speed), and we still reduce power. Can an engineer be twice as clever every two years? I would say this is unreasonable. We’re good, but we are not that good!
More than Moore
So, we come to “how can we keep this juggernaut going?” One approach has been to include new devices, and new materials, and new techniques into the mix. Micro-electromechanical systems (MEMS),
http://en.wikipedia.org/wiki/MEMS
die stacking, 3-D fabrication, and so on.
In effect, since the basic shrinking is an issue, what else can we integrate, and then start shrinking all over again? Again, is it possible to add to the base, and have the overall improvement be twice as good with every generation?
OK, So Where Are We Going?
I know I have posted on this subject before:
http://forums.xilinx.com/t5/PLD-Blog/Price-Perform
What is different, now? Right now, we are on the verge of a new generation of FPGA product introductions, either already announced, or soon to be announced by Xilinx and our competition.
I wish to thank all who replied, responded, and made suggestions. The success of this next generation will be partly due to you, our customers, who made sure that we knew what it was that you wanted.
Austin Lesea
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kcmman
- Ken Chapman holds a first class BSc Degree with honours in Electronic and Electrical Engineering from the University of Surrey. Before obtaining his degree, he spent 4 years working in production environments, making precision instruments and working his way through all levels of a small electronics company. He spent 4 years at Racal Radar Defense Systems combining detailed digital design with all aspects of system integration. Ken joined the UK division of Xilinx in 1991, and was instrumental in developing innovative methods of implementing DSP functions in the Xilinx devices. He has filed several patents while at Xilinx, including the 'MULT_AND' gate seen in each Virtex™ and Spartan-II™ device that has made multipliers and other arithmetic functions smaller and faster.
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peter.a
- Peter Alfke joined Xilinx in 1988 as director of applications engineering. He currently serves as Distinguished Engineer in the Advanced Products Group. He graduated in electronic engineering from the Technical University in Hannover, Germany in 1957. He went on to work in telecom and computer design with LM Ericsson and Litton Industries before moving to California in 1968. He has spent forty years in Applications Engineering with Fairchild, Zilog, AMD, and now Xilinx. He holds more than thirty patents, has authored many application notes, and given worldwide seminars on digital integrated circuits. He is active in the newsgroup comp.arch.fpga.
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austin.lesea
- Austin graduated from UC Berkeley in 1974 and 1975 with his BS EECS in Electromagnetic (E&M) Theory and MS EECS in Communications and Information Theory. He has worked in the telecommunications field for 20 years designing optical, microwave, and copper- based transmission systems. He developed SONET/SDH GPS-based Timing Systems for 12 of those years. For the last ten years at Xilinx, Austin was in the IC Design department for the Virtex product line. His new role is working for Xilinx Research Labs, where he is looking beyond the present technology issues.
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