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It Is All About Quality
WOW!
I knew we were good, but I didn’t realize how good we really are.
We have a number of reports about our quality online.
(See:http://www.xilinx.com/publications/prod_mktg/Quali
Besides the glossy pages, nice graphics, and our many standards certifications (certification is “we do” -- compliance is just “we try”) there is a much more compelling story (in my opinion): PPM.
PPM stands for parts per million. PPM defects are commonly used to describe how many parts are shipping that fail.
Here is where I was really impressed. In a recent period of review of our 65nm Virtex-5, FPGA family, quality, in shipments of 1.7 million parts, we had the following breakdown of real valid (actual) failures:
Assembly and Packaging: 1 PPM
Test Coverage: 3 PPM
Random Defect: 1 PPM
So what are these failures?
Packaging and assembly failures are commonly caused when a metal bridge or particle in the substrate that the die is mounted on causes the part to fail once it is soldered on to a customer board. Inspections and tests try to catch all problems before we ship, and the very few units that come back are used to improve those processes and improve the overall quality.
Test coverage is another area where we get failures: we just didn’t know how the part was going to be used so we did not test some tiny element. These are known as ‘test escapes’ in the business. One by one, we find the elements we did not test and add them into the test program. In doing so, the quality improves dramatically..
Random defects are just that: Random. They can be caused by some small particle on the die somewhere in the backend stack of metals and dielectrics, by a wire which has become too thin due to a particle that blocked the exposure for that mask, or by a particle landing across two wires, creating a short. At 65 nm, it is impossible to remove all particles from the process, and to the extent the fabricator misses a few particles and we don’t find them in test, they manifest themselves as failures as soon as the customer places the part on the board and loads their design.
Wait a Second: You MUST Get More Returns?
According to my colleague, there were about 8 times as many parts returned which had nothing wrong with them when tested, and another 8 times as many parts returned which were completely “toasted” – what we refer to politely as “electrical overstress” or EOS. There were also about 4 times as many parts where the customer destroyed the part (like smashing it to pieces). Last, there were about 5 ppm where the application of the product was such that the product did not work, and once this was pointed out to the customer (the part is not being used within the data sheet specifications), the parts now work.
The parts that were EOS basically show whole sections of the die that are completely destroyed. It may have been an electrostatic discharge (ESD) event, or it may have been an over-voltage spike on the power or IO: we will never know. We can make a guess from the area of the crater, and we can engage with the customer to suggest what might have happened, but we will never know. We do know that these sorts of EOS events are not a particle or random defect, as that signature is very different (basically: no large crater!).
The engagement with the customer who returns the part is critically important: they learn how to properly use the part, and their costs decrease because they are not throwing perfectly good parts away. Sometimes the solutions to these problems are as simple as “the assembly process is not meeting our requirements for the solder reflow profile” or some other easy-to-fix issue.
If a customer is stressing the parts and blowing them out, it is also important that we help them learn what ESD assembly rules they must follow as well as help them make sure their power supply systems are meeting our specifications.
Bottom line: quality is a feedback system. And when it is properly implemented, it drives the defects to 0. When it works, it is a beautiful process.
Austin Lesea
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kcmman
- Ken Chapman holds a first class BSc Degree with honours in Electronic and Electrical Engineering from the University of Surrey. Before obtaining his degree, he spent 4 years working in production environments, making precision instruments and working his way through all levels of a small electronics company. He spent 4 years at Racal Radar Defense Systems combining detailed digital design with all aspects of system integration. Ken joined the UK division of Xilinx in 1991, and was instrumental in developing innovative methods of implementing DSP functions in the Xilinx devices. He has filed several patents while at Xilinx, including the 'MULT_AND' gate seen in each Virtex™ and Spartan-II™ device that has made multipliers and other arithmetic functions smaller and faster.
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peter.a
- Peter Alfke joined Xilinx in 1988 as director of applications engineering. He currently serves as Distinguished Engineer in the Advanced Products Group. He graduated in electronic engineering from the Technical University in Hannover, Germany in 1957. He went on to work in telecom and computer design with LM Ericsson and Litton Industries before moving to California in 1968. He has spent forty years in Applications Engineering with Fairchild, Zilog, AMD, and now Xilinx. He holds more than thirty patents, has authored many application notes, and given worldwide seminars on digital integrated circuits. He is active in the newsgroup comp.arch.fpga.
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austin.lesea
- Austin graduated from UC Berkeley in 1974 and 1975 with his BS EECS in Electromagnetic (E&M) Theory and MS EECS in Communications and Information Theory. He has worked in the telecommunications field for 20 years designing optical, microwave, and copper- based transmission systems. He developed SONET/SDH GPS-based Timing Systems for 12 of those years. For the last ten years at Xilinx, Austin was in the IC Design department for the Virtex product line. His new role is working for Xilinx Research Labs, where he is looking beyond the present technology issues.
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