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Power to the PCB!
Recently, the Virtex®-5 Printed Circuit Board (PCB) Designers Guide was revised and updated to reflect a great deal of work on the bypass or decoupling networks we recommend.
http://www.xilinx.com/support/documentation/user_g
What do these changes mean for you, the customer?
Fewer Caps
Quite simply: What these changes mean are fewer components. How can this be? If we were recommending more capacitors for power supply decoupling in the past, why are we able to now recommend fewer capacitors?
The answer is: A lot of hard work, both in simulations, and building typical stack-up boards, and testing these in the labs here at Xilinx.
The Magic is in the Sparse Chevron™ Packaging
In Virtex-4, we worked with outside consultants and industry experts to provide a package that could deliver the kind of performance our customers were demanding (here detailed for the Virtex-5 family):
The key to this breakthrough is to reduce the magnetic coupling in the return currents from switching to and from IO pins to and from power and ground pins. The net result is less switching noise, or less ground and Vcc ‘bounce.’ Part of this solution was choice of an optimal set of capacitors in the package itself, where they are able to do the most good.
The first thing you will notice is that the small packages still require many external capacitors. That is because the small packages have no room for on-package capacitors, and on-package capacitors have the least benefit for these small packages. The medium to large packages all benefit tremendously from having capacitors on the package substrate, right next to the flip-chip die.
The Bottom Line
The result of all this engineering to reduce the physical size of the current loops formed, and to bypass the transients close to their generation, is that the need for external PCB mounted capacitors diminishes quite substantially.
The net result from this work is fewer external components required, all based on results that were carefully thought through, and then actually verified on a package by package basis.
Austin Lesea
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kcmman
- Ken Chapman holds a first class BSc Degree with honours in Electronic and Electrical Engineering from the University of Surrey. Before obtaining his degree, he spent 4 years working in production environments, making precision instruments and working his way through all levels of a small electronics company. He spent 4 years at Racal Radar Defense Systems combining detailed digital design with all aspects of system integration. Ken joined the UK division of Xilinx in 1991, and was instrumental in developing innovative methods of implementing DSP functions in the Xilinx devices. He has filed several patents while at Xilinx, including the 'MULT_AND' gate seen in each Virtex™ and Spartan-II™ device that has made multipliers and other arithmetic functions smaller and faster.
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peter.a
- Peter Alfke joined Xilinx in 1988 as director of applications engineering. He currently serves as Distinguished Engineer in the Advanced Products Group. He graduated in electronic engineering from the Technical University in Hannover, Germany in 1957. He went on to work in telecom and computer design with LM Ericsson and Litton Industries before moving to California in 1968. He has spent forty years in Applications Engineering with Fairchild, Zilog, AMD, and now Xilinx. He holds more than thirty patents, has authored many application notes, and given worldwide seminars on digital integrated circuits. He is active in the newsgroup comp.arch.fpga.
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austin.lesea
- Austin graduated from UC Berkeley in 1974 and 1975 with his BS EECS in Electromagnetic (E&M) Theory and MS EECS in Communications and Information Theory. He has worked in the telecommunications field for 20 years designing optical, microwave, and copper- based transmission systems. He developed SONET/SDH GPS-based Timing Systems for 12 of those years. For the last ten years at Xilinx, Austin was in the IC Design department for the Virtex product line. His new role is working for Xilinx Research Labs, where he is looking beyond the present technology issues.
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