- Xilinx User Community Forums
- :
- PLD Blog
- :
- Spring Is Here!
Announcements
--- Win Prizes for Kudos! ---
From now on, every time you provide a good solution or post valuable information on Xilinx User Community Forums, you will be awarded Special Kudos by the Forum Administrators. Every six months, the top two Kudos winners will receive a very special prize from Xilinx!
So, for a chance to claim your well-earned reward, please continue to reply to questions and post elite messages on our Forums. Your contributions are always appreciated!
Spring Is Here!
Spring Is Here!
Going to Daylight Savings Time a few weeks ago was harder for me than I recall it being: my alarm clock sounds at 5:45 a.m. during the work week, so I may get to work before the roads become parking lots.
Along with Spring, we have the announcement of Virtex®-6, and Spartan®-6 product lines:
http://www.xilinx.com/products/devices.htm
Watching a new product release happen is really amazing. In my ten years as an IC designer, I personally participated directly in seven of those releases. Now that I am in Xilinx Research Labs, I have a different view of the process. Even from this point of view, it is still fun to watch.
As mentioned in the previous blog:
I hope that we listened well to your needs, and deliver the best that the technology has to offer.
The Rise of Serial
You will notice that the Spartan®-6 family now has “low-speed” gigabit transceivers: by adding these transceivers to the low-cost family, I think it is safe to say that such technology has been embraced by designers and architects, and that it is not considered unusual any longer.
In both lines, applications for these serializer/deserializers range from networking to video.
http://www.xilinx.com/publications/prod_mktg/Virte
DDR Keeps on Truckin’
As well, since just about every FPGA application now requires a small farm of DDR2 or DDR3 memory devices to live next door, we have added features to the silicon to improve performance, and make the interfacing even easier.
For 40 Gb/s and 100 Gb/s networking applications, having transceivers is not enough: one must also have the necessary memory bandwidth to accomplish something useful with all those bits flying to and fro.
The Sun Will Come Up, Tomorrow
So, as I celebrate the first day of Spring, I look forward to waking up in the light (again). Now it is time for me to get another cup of coffee, and start my day here at work.
Austin Lesea
-
kcmman
- Ken Chapman holds a first class BSc Degree with honours in Electronic and Electrical Engineering from the University of Surrey. Before obtaining his degree, he spent 4 years working in production environments, making precision instruments and working his way through all levels of a small electronics company. He spent 4 years at Racal Radar Defense Systems combining detailed digital design with all aspects of system integration. Ken joined the UK division of Xilinx in 1991, and was instrumental in developing innovative methods of implementing DSP functions in the Xilinx devices. He has filed several patents while at Xilinx, including the 'MULT_AND' gate seen in each Virtex™ and Spartan-II™ device that has made multipliers and other arithmetic functions smaller and faster.
-
peter.a
- Peter Alfke joined Xilinx in 1988 as director of applications engineering. He currently serves as Distinguished Engineer in the Advanced Products Group. He graduated in electronic engineering from the Technical University in Hannover, Germany in 1957. He went on to work in telecom and computer design with LM Ericsson and Litton Industries before moving to California in 1968. He has spent forty years in Applications Engineering with Fairchild, Zilog, AMD, and now Xilinx. He holds more than thirty patents, has authored many application notes, and given worldwide seminars on digital integrated circuits. He is active in the newsgroup comp.arch.fpga.
-
austin.lesea
- Austin graduated from UC Berkeley in 1974 and 1975 with his BS EECS in Electromagnetic (E&M) Theory and MS EECS in Communications and Information Theory. He has worked in the telecommunications field for 20 years designing optical, microwave, and copper- based transmission systems. He developed SONET/SDH GPS-based Timing Systems for 12 of those years. For the last ten years at Xilinx, Austin was in the IC Design department for the Virtex product line. His new role is working for Xilinx Research Labs, where he is looking beyond the present technology issues.
- Package Generated Alpha Particles: They are a Pro...
- Helping the Customer Drive to ‘Zero Defects’
- Targeted Platform Design
- It Is All About Quality
-
The ‘Programma
ble Imperative ’ -
Reliabilit
y - A True Winning Number Generator
- Spring Is Here!
- Happy New Year: Moore, More Moore, and More than ...
- SEU, Not Again!
-
austin.lesea
on:
SEU, Not Again!
- larthe on: Estimating Average Switching Rates
-
fpgasdr
on:
FIFOs, A Tutorial Descriptio
n -
gszakacs
on:
Terminatio
n is Never Easy -
austin.lesea
on:
Power to the PCB!
- tocktock on: Finding Stuff: Part 2
- seamusbleu on: Using Self Scanning Memory for State Machines
- brouhaha on: Finding Stuff
-
kcmman
on:
That Dangerous Asynchrono
us Reset! - q on: Quadrature Decoding with Resolution Options
