PLD Blog

The first omission is probably the most common: the configuration signals are somehow completely ignored when it comes to signal integrity engineering analysis. Why? Probably because in the past, it worked, and no one pays any attention to anything that has worked in prior designs. Why look at it again? The rise and fall times of the drivers used for the configuration interfaces, either on the Xilinx^® FPGA, on external components, continues to get faster as the technology nodes get smaller. Faster rise and fall times mean more sensitivity to mismatched impedances, and may require series or parallel termination schemes (or both).

Next most common are the distribution of the differential clocks to the various global clock inputs, and reference clock inputs for the MGT’s. These high-frequency signals usually have very fast rise and fall times, and are thus very sensitive to not only the impedances of the lines, drivers, and receivers, but also to differential length matching. If the (+) input line is longer than the (-) input line in the differential pair at the receiver, there can be significant pulse distortion. In addition, the differential signaling standard is not a buss: it is only optimal for point-to-point connections. If you need to form a buss, you will have to pay special attention to the lengths, and where the terminations are placed. A differential buss may always be a compromise, and lead to worse signal integrity.  Worse signal integrity will result in jitter on these interfaces, which will degrade the bit error rate performance of the MGT’s and perhaps even lead to bit errors in the data being processed inside the FPGA device.

In Virtex^®-5, the MGT’s are provided in pairs, with a common VCO for transmits, and receives. This results in a more efficient (lower) power performance, but requires that the pairs have the same reference clock rates. Generally speaking, the ferrite beads and capacitor networks on the analog supplies are required to isolate the MGT’s from noise on the board, and also to isolate MGT’s at different rates from each other. If all the MGT’s share the same rates, then some commonality of the analog power may result in a savings on the number of ferrite beads that are used. Please consult with your Xilinx FAE to learn about the best practices that we use on our own development boards.

Summary

Three simple things that should be covered by some signal integrity analysis have been detailed above: do not forget the configuration pins, simulate the clock distribution schemes, and check on the rates of the MGT’s and examine if the analog powering may be able to share some ferrite bead isolation.

Some references are listed below to aid you:

GTP: