PLD Blog

[#1]

What do you want?

I have been watching the forums, and answering the questions I know something about as they pop up.  But, I usually find a pattern to the questions, and that then inspires me to provide a blog which addresses the issue.

So Here is the Problem

There is a pattern to what I would refer to as “people who are new to FPGA devices” who have a classic set of questions:  How do I program the device?  How does one achieve timing closure?  What I/O standards do I use? And so forth.  I would encourage those who are new to FPGA devices to spend a little more time using your favorite search engine to read the technical answers.  There is a tremendous amount of “stuff” out there.  I apologize if it seems that there is so much there and you cannot easily find what you are looking for.  Xilinx is more than 25 years old (first parts shipped in 1985).

What does the community feel a need to know more about?

 What would help you get your job/project done faster?

I do have a “real job” here at Xilinx, in Xilinx Research labs; but, as I am the lone blogger, I also have a responsibility to you, our customers, to help you “get it done.”

For Getting Started with Xilinx please refer to the “Getting Started” section of Xilinx.com: http://www.xilinx.com/company/gettingstarted/

Here you will find information about:

• FPGA Basics
• FPGA versus ASIC
• CPLD Basics
• Designing with CPLDs
• Xilinx Offerings
• Additional Resources

[#2]

It would be nice to compile a real FAQ list, not just on questions about how to use the forums. This could easily be harvested from the existing forum posts, and the answers could also come from answered threads as well as links to the appropriate documentation. -- Gabor

[#3]

Gabor,

Thanks!  Not a bad idea:  harvest what the most commonly posted questions are in the forums.

Hmmm.  I'll have to think how that can be done.

[#4]

How about special 'rooms' / 'compartments' (or whatever you call them) in the Forum dedicated to one-way feedback. i.e.,

Errata for Xilinx documents

Errata for www.xilinx.com and all sub-pages therein

Suggestions for Xilinx documents

Suggestions for www.xilinx.com and all sub-pages therein

Suggestions for Xilinx S/W tools (ISE, XST, CSP, iMPACT, etc.,)

Suggestions for Xilinx H/W tools (JTAG pods, demo/eval boards, etc.,)

Suggestions for Xilinx FPGA silicon

Suggestions for Xilinx CPLD silicon

Suggestions for Xilinx configuration silicon

(a) These are things I'd feel a little guilty bothering Webcase tech support people who are under the gun to solve real problems, not no-big-hurry suggestions or long-range planning issues.

(b) By putting this in Forums, users can 'crowd-source' best recommendations to Xilinx.

(c) Some Errata / Suggestions may need graphics to explain a concept. Is there a way to upload powerpoint, word, excel, canvas, jpeg files, etc., for all to see? What about collective editing?

[#5]

l,

Good ideas.  Thank you.  Working on them right now.

[#6]

Also need to consider how to "retire" Errata that have been fixed and Suggestions that have been implemented (to avoid wasting the time of future visitors that could stumble into such threads).

Maybe add (read-only, not open to new posts?) sub-folders called "Retired" underneath the main categary folders I outlined above.

[#7]

l,

Right now, we do not really have any way to filter the forum posts.  Perhaps a few hours with som Perl scripts would do the job, but the software we use doesn't really have what is needed for effective filtering of posts to gather useful 'stuff.'

So, while I wait to see what can be done there, we can use the webcase system to gather the top 25 (or whatever) issues/problems and their solutions.  If do read very fast, so I don't mind reading an already sorted list so I know what is getting the most 'clicks.'

The other thing I am working on is a place for beginners (a forum section which is dedicated to 'newbies') so that they have a place that is more supportive (most of the working 'rank & file' engineers have little patience for those who are just getting started).

I have a meeting next week to discuss all the items that have been submitted with the web team.

Keep those suggestions coming!

[#8]

Austin,

What I most often struggle with, and what I most often see others struggle with on real projects, is timing constraints. 

There are some excellent timing resources available, in particular the "cookbook" portion of the Timing Constraints User Guide and your own Timing Constraints tutorial here. However, what I often find missing in all of these tutorials and guides is the connection between the code, the timing report, and the constraints. 

I don't know what the best way is to unify the various concepts involved. For me, I think that would be a guide with more examples that relate the code in non-trivial designs to the proper constraints through the timing report.

That would be one approach, create a new document which clearly pulls all these things together. There are plenty of application note designs that would suffice, or eval board demos, which do not include proper constraints (which is extremely frustrating!). I would start with no constraints, run the tools, and build up to a properly constrained design.

Part of this is explaining the the timing reports in detail. This post has the sort of explanation I'm talking about. gszakacs's comments helped me immensely. I find that some of the language in the guides and timing reports is confusing/miseading.

This would be a hard document to create. That's probably why the current documentation deals largely with pieces and mostly abstractions. I think that's probably why it's so hard to relate back to a real design. In a real design, you have no choice but to go through all the steps together as a whole. The documentation generally discusses only one specific aspect while abstracting several others. As a poor analogy, discussing how to play the tuba well versus composing a symphony.

What are your thoughts here?

[#9]

d,

Getting the timing constraints right are probably the biggest part of any project.  My blog postings on timing constraints is just a beginning:  the references given should all get read through, and all the exmples tried on a sample project.

The same constraints for one project may be entirely different on another project.  Coding styles vary, and requirements are different.  The timing for a LTE basestation are totally different from a MicroBlaze with various peripherals, running Linux.

Generally speaking, in hardware design, there are no abstractions, and no shortcuts:  you start at the beginning, and work until the end.  Often 90% of the actual work is getting the design right, and getting it to meet timing with sufficient slack.

Not sure how to help you here:  at the end of one project, you will probably not need what you are asking for, and you will become enough of an expert to answer the questions of others.

[#10]

hi dis s aravind doing final yr BE(ECE)...i am in need of help for doing my sem project...my project s on BIST(vlsi)... i need to write verilog code for the following circuit...but the only change s i use a 3 bit adder instead of dis CUT...pls reply if someone can help with dis... thank u :)

[#11]

Austin --

Would it be correct to assume that the ideas in my post of  01-24-2012 06:09 PM will take some time to come to fruition ..... and that I/we should just dump our suggestions into the Webcase queue?

[#12]

l,

Correct.  But I would encourage you to post any ideas right here.  All ideas posted here automatically sends an email to me, and the forum team.  I, and they, are reading every one of them.

We have met and discussed a number of the ideas.  The team is now in the process of implementation of the first one of those.

All ideas are very welcome.  However, the previous post before yours does not pertain to the subject at hand, and should have been asked in the appropriate forum:  for that I have no solution!  Please post appropriate suggestions here, and post your problems and questions on the forums, or open a webcase.

We are working on the top 3 ideas, and it will not happen instantly.  Some ideas can't be implemented in the given software (right now), but that doesn't mean we aren't asking the providers of the platforms (Lithium, etc.) to respond to the requests: we are.

[#13]

http://www.xilinx.com/products/boards-and-kits/index.htm

Some of the Xilinx FPGA demo/eval boards I've had in the past included schematics that failed to have auto-zone bubbles to tell the user where intra-page connectors are going.

This wasn't just annoying, but also very surprising .... that there could even exist a schematic-capture tool of recent vintage that didn’t have an auto-zone-bubble-creation feature.

In any case, suggest adding this as a line item on Xilinx' FPGA demo/eval board pre-release peer-review checklist.

Also, a competitor FPGA company (starts with an L), uses block-based/hierarchical PWB schematics . . . . not a fan of those, either, as PWBs are, by definition & in practice, one level. Would rather have flat schematics with auto-zone bubbles.

[#14]

Referring to Figure 6 on page 11 .....

http://www.xilinx.com/support/documentation/data_sheets/ds123.pdf

.... and the description/definition of spec TOER on page 13 implies that this applies to just the pins INIT\ (FPGA) & OE/RESET\ (config PROM). This is misleading. Configuration can be held off by holding PROG\ (FPGA) & CF\ (config PROM) low just as easily. The spec should be updated to make it clear that the holdoff-until-VCC-ready scheme applies to both.

[#15]

Open FPGA Editor.

Press Cntl+F.

The resulting dialog box has a "Find What" pulldown menu.

We recommend:

a) Replace the pulldown menu with a pick-one-of-N radio button, but also include an option (default) for ANYTHING:

     Arc
     Bel
     Component
     Hard Macro
     Net
     Site
     Site/Comp Pin
     Wire
     ANYTHING

b) When the mouse cursor hovers over the text for each radio-button option, FPGA Editor should launch a ‘pop-up’ text bubble that summarizes what this category means (the text bubble disappears when the mouse cursor moves off the text). Designers think in terms of CLBs, slices, BRAM, DCMs, nets, IOBs, etc., .... many of us have a difficult time keeping track of what the hell a "bel" or "hard macro" is, or the difference between an arc / net / wire (one or more of them is equivalent to a stub?), etc., etc.,

Constantly referring back to the FPGA Editor Help Glossary (which currently doesn't have half these terms defined) isn't the best solution. "On the spot" help w/ these hypothetical ‘pop-up’ text bubbles (I'm seeing advertisements like this on my Microsoft Internet Explorer all the time these days <knashes teeth>) is, I think, the way to go.

[#16]

Subject: JTAG pods

Some military / government customers operate secure labs that have strict rules about devices with non-volatile memory that enter and (more importantly) exit the lab.

They need some documents that either

     [1] Assure them that nobody can write classified data to non-volatile (EEPROM or Flash) memory in your JTAG pods and walk out of their lab with it, or

     [2] Describes how to clean your JTAG pods to ensure that no such data goes with it.

It would be nice to have a hyperlink on this page ....

http://www.xilinx.com/products/boards-and-kits/HW-USB-II-G.htm

.... to the applicable supporting documentation:

     a) Letter of Volatility from the manufacturer which describes

          All memory components in the hardware

          How they can & can’t be written-to

     b) Sanitization Procedure that describes how to clear all memory components

Sometimes these issues crop up at the 11th hour, and we need some answers (i) right away, and (ii) that are un-mistake-ably from the manufacturer (Xilinx). Having this on the website satisfies both criteria in a way that sending email asking an FAE to fetch PDF docs (that may or may not be up to date) does not.

[#17]

StateCAD was a nice little tool that I used to use quite a bit (maybe I was the only one), but during a hiatus from FPGA design for a few years, seems to have disappeared from recent ISE releases.

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  1
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Poking around the Xilinx website reveals ....

http://forums.xilinx.com/xlnx/board/crawl_message?board.id=DEENBD&message.id=1245

If possible, recommend updating ....

http://www.xilinx.com/support/answers/32805.htm

.... with info answering:

1a) What does "StateCAD got deprecated" mean?

abandoned?

sold to another company? . . . and what company (if Xilinx has no plans to compete in that part of the design space)?

The definition here

http://dictionary.reference.com/browse/deprecate

doesn't make sense. Can't help wondering if this AR fell through the proof-reading cracks.

1b) Is Xilinx planning a replacement product for StateCAD? If not, any recommendations for 3rd-party tools that do a similar job? i.e., Synopsys Synplify-Pro synthesis tool can display FSMs graphically

1c) There's nothing wrong with Xilinx exiting the market for certain kinds of (obscure/niche) EDA tools .... but doing so always begs the obvious question: "Where did that tool and/or market go?"

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  2
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Feature enhancement recommendations if StateCAD should get resurrected (or Xilinx or whoever might be working on a replacement tool) ....

StateCAD could only import *.dia files (previously-generated state diagrams from StateCAD). Would be more useful if next-gen StateCAD could:

a) also import FSMs from HDL text files [ my_FSM.v Verilog module or my_FSM.vhd VHDL entity/architecture ] and draw a bubble diagram from them.

b) analyze the FSM for conflicting state transitions, lock-up states, unreachable states, etc., .... though this is a considerable effort that encroaches on Spyglass' territory. i.e., We'd be stunned (but pleasantly stunned) if any FPGA vendor took such a minor CAD tool that far.

[#18]

As far as I know, the Xilinx UCF format demands that each IOB attribute be preceded with the signal name:

NET "tp_0_6"               LOC = "D22"  ; NET "tp_0_6" IOSTANDARD = LVTTL  ; NET "tp_0_6" SLEW = FAST  ; NET "tp_0_6" DRIVE = 24  ;

This exposes the design to flaws caused by typos & misqueues with drag-n-drop copy-n-paste. We'd like to be able to specify various attributes of an FPGA I/O pin citing the signal name just once (one "NET" declaration at the beginning and one semi-colon at the end, attributes separated by white-space or commas, or whatever):

NET "tp_0_6"               LOC = "D22"   IOSTANDARD = LVTTL  SLEW = FAST  DRIVE = 24  ;

If modern synthesis tools can do that ....

 /* synthesis syn_srlstyle = "registers" syn_allow_retiming = 1 */

 /* synthesis xc_props = "CLKDV_DIVIDE          = 4, \
                          CLKIN_DIVIDE_BY_2     = FALSE, \
                          DLL_FREQUENCY_MODE    = LOW, \
                          DUTY_CYCLE_CORRECTION = TRUE" \
 */ ;

.... why can't  *.ucf FPGA constraint formats?

[#19]

Whenever a new FPGA family comes out, we get the usual trumpeting of features, 500+ page data sheets, 500+ page users guides, etc., . . . . but for those of us already very familiar with the immediate predecessor families, it would be vastly easier if we saw some 1-3 page bulleted list of "deltas". i.e., show us only what changed about this new family with respect to its' antecedents.

I don't recall seeing any such documents in the past, and I get the feeling that marketing people seem to think that presenting something "new" in the light of something "old" is somehow uncomplimentary to the former, when personally, I think it's more comforting.

[#20]

From within ISE, go to "Help" ---> "About...".

The resulting "About Project Navigator..." dialog box itemizes

     Release Version
     Application Version
     (and some some copyright info)

Yet, the “What is your environment?” part of the WebCase form wants to know

     Software Version
     Service Pack

The info in the "About Project Navigator..." dialog box should match what (and use the same nomenclature as) the WebCase form wants to know.

[#21]

From within ISE, go to "Project" ---> "Cleanup Project Files...".

We're then given a dialog box showing us a list of files asking us if we "want to continue".

a) Yes, we always want to continue! Would like to see a "Don’t show us this again" checkbox here so that we can avoid dealing with this window every time. ..... or make that a User’s Choice in a Preferences/Option menu.

b) The ASCII characters in that list of files can be highlighted, but it isn't clear what highlighting them means. Parts of a file name can be highlighted, and parts remain UN-highlighted ..... in any case, highlighting or UN-highlighting (completely or partially) doesn't seem to exert any control over which files get erased & which don't. We'd rather select all that in some options/preferences menu, either globally or on a project-by-project basis, anyway.

c) Would be nice to have a hotkey ("F5") that launches & executes File Cleanup w/o going through the "Project" ---> "Cleanup Project Files..." every time.

[#22]

Every projects' *.mrp file has a section called "Design Summary" that itemizes what percent of the FPGA's Used Resources are consumed by this design.

Unfortunately, it doesn't tell you anything about the FPGA's UN-Used Resources. i.e., if this particular design doesn't use any BlockRAM, it doesn't even remind us that there is such a resource available.

The *.mrp report files should tell us the percent we're using of ALL the resources on the chip, even if they're unused.

It would be good for marketing & innovation to remind designers of (impressive) resources on the FPGA that they could be using. This might spur ideas for new features in the existing design and/or ideas for future designs.

[#23]

The timing results in the *.PAR file come out sorted by worst margin to best margin.

Consider adding an option (via the preferences menu?) to choose between sorting them

     (a) that way
     (b) alphanumerically
     (c) listed in the same order as they occur in the *.UCF file.

[#24]

Sometimes in building a new design, P&R fails to run due to unlocked I/O, with the following error message .....

      INFO:Place:834 - Only a subset of IOs are locked.
      Out of 273 IOs, 256 are locked and 17 are not locked.
      If you would like to print the names of these IOs, please
      set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
      ERROR:Place:207 - Due to SelectIO banking constraints,
      the IOBs in your design cannot be automatically placed.

Instead of asking users to set some obscure XIL_PAR_DESIGN_CHECK_VERBOSE environment variable, why not just:

a) list (at the point where this error message kicks in) the unlocked I/Os that ISE is unhappy with.

 .... or, if that would make that report too big & unwieldy:

b) always dump the unlocked I/O list to a stand-alone text file (either with a special, Xilinx-defined 3-digit file extension or a simple text file "MYDESIGN_unlocked_IO.txt"). That way, you don't clutter the *.par file, while at the same time making the information available when needed without the user having to jump through hoops to get it. The error message in the *.par file could change to:

      INFO:Place:834 - Only a subset of IOs are locked.
      Out of 273 IOs, 256 are locked and 17 are not locked.
      If you would like to examine the names of these IOs, please
      refer to file ____________.___ available in the same directory
      as this *.par file.
      ERROR:Place:207 - Due to SelectIO banking constraints,
      the IOBs in your design cannot be automatically placed.

[#25]

The P&R process produces a large number of files & reports (text & html). In one of them, it should give a clear summary of each IO bank on that FPGA, including, but not limited to:

  (a) Vcco voltage required in each bank,
  (b) if VREF pins are being used in a given bank (and what value VREF should be set to on the PWB)
  (c) what I/O standards are used in each bank (LVTTL, LVDS, LVPECL, etc.,)

Example:

Bank #      Vcco         Vref    Logic Standards Used
-----------------------------------------------------
0           3.3v      user I/O   LVTTL
1           2.5v      user I/O   LVDS
2           3.3v      user I/O   LVTTL, LVCMOS33
3           2.5v         1.25v   SSTL2_I, LVDS
4           1.8v         0.90v   HSTL_II_18, SSTL18_I
5           3.3v      user I/O   *** none (bank I/O unused) ***
6           1.5v         0.90v   HSTL_IV
7           2.5v         1.25v   SSTL2_I, LVCMOS25

[#26]

@ lenihan3we

You can put multiple IO attributes in one line separated by the pipe operator (|). e.g.

NET "tp_0_6"               LOC = "D22"  | IOSTANDARD = LVTTL  | SLEW = FAST | DRIVE = 24  ;

>by lenihan3we on 02-19-2012 08:28 PM

>As far as I know, the Xilinx UCF format demands that each IOB attribute be preceded with the signal name:

>NET "tp_0_6"               LOC = "D22"  ; NET "tp_0_6" IOSTANDARD = LVTTL  ; NET "tp_0_6" SLEW = FAST  ; NET >"tp_0_6" DRIVE = 24  ;

[#27]

Go to pages 24 & 25 of this document ....

http://www.xilinx.com/support/documentation/data_sheets/ds083.pdf

Note that Tables 8 & 9 describe single-ended and differential I/O standards.

We suggest that these tables be expanded (even if it means presenting them in landscape orientation) to include columns describing

     which I/O standards support DCI (inputs? outputs? tri-stated outputs? bidirects?) and
     which I/O standards support DDR (inputs? outputs? tri-stated outputs? bidirects?)

That means Table 10 would essentially be absorbed into Tables 8 & 9.

We know Virtex-II-Pro is obsolete. We're just using this as an example. The principle can still apply to more recent FPGA families.

The idea is to provide one-stop shopping for a summary of what we need to know about I/O types.

In a related vein, note that page 224 of .....

http://www.xilinx.com/support/documentation/user_guides/ug012.pdf

..... does NOT begin by itemizing which I/O standards (and directions) for this particular FPGA family support DCI. This is job #1 before learning more about DCI.

[#28]

Suggest that every FPGA family have a "FAQ" document. They're especially good for issues that are hard to stick into one bin (i.e., does the following belong in the I/O section or packaging section?).

Q: We will be designing an FPGA with a large BGA package that has many more balls than our mission-logic I/O needs. It turns out we will have 100's of general-purpose I/O pins that have no tactical place to go. What should we do with them?

     ___ Ground them
     ___ Let them float
            If float, do we even need a solder pad on the PWB for the balls to "land on” for use
               ___ in enhancing mechanical/vibration stability
               ___ as a thermal path to bring heat out of the FPGA

[#29]

Another "FAQ" question ...

When we go through the "New Project Wizard - Import EDIF/NGC Project", we find "Copy the input design to the project directory." and "Copy the constraints file to the project directory." checkboxes.

Why are these automatically checked?
Why do they even exist?
What purpose does it serve to copy these files?
     (floating the mouse over the checkboxes should produce a pop-up balloon explaining the answers to these questions)

[#30]

It seems pertinent to add to this Blog, that the WebCase portal is the best channel for providing feedback to the Technical Support team. There are no guarantees or service levels associated with the Xilinx Forums or PLD Blog.

If you find a bug, WebCase is absolutely the correct channel to use, as our Technical Support Organisation is only permitted to create  a Customer Found Change Request (bug) if there is a WebCase number associated with it.

In addition, if you have general feedback about anything on Xilinx.com, please feel free to use the "Feedback" link at the bottom of every page.

It will take you to this form into which you can enter your comments. This form will then get sent to the appropriate team/person, based on the nature of your comment.