PicoBlaze

[maverick_fc]

Hi all,

Please help me as I'm doing research.

I want to design ADC using picoblaze. My idea of implementation goes this way:

1. Intialize bus signals
2. Read A/D channel value and store it in scratchpad memory
3. Software for A/D communication           

Code

-------

; Constant Definition
adc_conv            EQU       $01
sck                       EQU       $01
adc_lsb               EQU       $00     ; A/D Channel value LSB    
adc_msb            EQU       $01     ; A/D Channel value MSB   

; Port Mapping

ctrl_port             DSOUT        $02

initialize:    LOAD      s0, $00
                    LOAD      s1, $00 

                   LOAD      s2, $00 

                    LOAD      s3, $00

                    LOAD      s4, $00

                   LOAD      s4, $00

                    ;Vref = 101110111000  = 3 volts = 3000 millivolts in  binary representation
                    ; Vin = Vref - 1LSB = 0000_1011_1011_0111 = BB7 hex
                    ; Vin_low = B7 hex
                    ; Vin_high = 0B

                     FETCH     s2, adc_lsb

                     FETCH      s3, adc_msb

                    LOAD        s4, $B7
                    LOAD        s5, $0B             

read:           XOR           s0, adc_conv     
                    OUT           s0, ctrl_port     
                    XOR           s0, adc_conv  
                    OUT           s0, ctrl_port
                    LOAD         s1, $20            

                     OUT          sA, o_l

                     OUT          sB, o_h
next_bit:      XOR            s0, sck         
                      OUT            s0, ctrl_port    
                      XOR          s0, sck     
                     OUT            s0, ctrl_port                       

                     SLA           s4

                     SLA           s5

                     LOAD     sA,s4

                     LOAD    sB,s5

                     SUB          s1, $01      
                    JUMP       NZ, next_bit                        

                     RET                                     

ADC specs:

16-bit, 0-3V full scale voltage input, Vin = Vref - 1 LSB

Please help me to acheive the required design.

I have gone through reference design shown below.

Reference Design: http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm

                              PicoBlaze Processor Amplifier and A/D Converter Controller

But I didnot understand how output is generated.

Please please help.

[eteam00]

Maverick_tc,

Are you interested in learning how to design and write picoblaze code, or do you simply want someone to design and write your code for you?

For example, if you were asked to point out which picoblaze instruction reads the A/D serial data, could you do that?

My guess (based on this latest posting, as well as your previous postings) is that you cannot point out which picoblaze instruction reads the A/D serial data, which means that you don't really understand how picoblaze (or perhaps FPGA in general) works.  So you then have two logical choices:  learn, or find someone to do it (the design) for you.

There is no shame in asking for help, I ask for help all the time.  It's important, however, to understand what sort of help you need and what sort of help you are willing to accept.

Regards,

Bob Elkind

[maverick_fc]

Is my assumption(STEPS) wrong ?

I think I don't need any shift registers since all the operation will be done by ADC.

I just need to write serial data communication between control signals of ADC.

Is it all?

Then the work flow looks like:

1. conv is high for starting conversion

2. data is set to a/d channel value

3. conv made low for serial data transmission

4. On appropriate rising edge of clock, sck, transmit data.

Are the above steps correct for this design ?

Since, I give voltage input from a function generator to adc, do the above steps 1,2,3,4 are valid for adc control mechanism ?

Input/Ouput waveform is observed from CRO.

Please please help.

[maverick_fc]

Please look at this code for ADC_CONTROL i.e., 16-bit data input, sck (shift clock 32KHz), conv (1KHz signal).

I have enclosed assembled code for adc controller.

Please comment.

[eteam00]

Maverick,

The code you posted is the wrong code.

You haven't responded to my previous guidance in this thread in a way that suggests you understand either the code you posted or even the basics of PicoBlaze, FPGAs, and ADCs.

Going from generating simple output pulses to controlling an ADC is a huge jump, and I don't think you are up to it quite yet.  Learning this stuff on your own is not easy, it takes considerable effort, and this is a line of work that doesn't necessarily suit everyone well.

I don't have any easy answers for you.  You've said you are a programmer, not a hardware designer.  If you are interested in HW design, you should go to school or work somewhere there are hardware designers to guide you and instruct you.

We (in this forum) could walk you through every problem and skill along the way, and it would take many weeks to complete a project, and where would this leave you at the end?  You have much to learn, and this forum is not an efficient venue for training new hardware designers.

- Bob Elkind

[maverick_fc]

Hi Bob,

Serializing data is bit-by-bit input and deserializing its vice-versa.

Modified Code of ADC looks like this:

; Port Mapping
sd0_0               DSIN      $00                 ; serial data input bit 0
sd0_1               DSIN      $01                 ; bit 1
sd0_2               DSIN      $02                 ; bit 2
sd0_3               DSIN      $03                 ; bit 3
sd0_4               DSIN      $04                 ; bit 4
sd0_5               DSIN      $05                 ; bit 5
sd0_6               DSIN      $06                 ; bit 6
sd0_7               DSIN      $07                 ; bit 7
sd0_8               DSIN      $08                 ; bit 8
sd0_9               DSIN      $09                 ; bit 9
sd0_10              DSIN      $10                 ; bit 10
sd0_11              DSIN      $11                 ; bit 11
sd0_12              DSIN      $12                 ; bit 12
sd0_13              DSIN      $13                 ; bit 13
sd0_14              DSIN      $14                 ; bit 14
sd0_15              DSIN      $15                 ; bit 15

signal1             DSOUT     $00                 
signal2             DSOUT     $01                 

start:              LOAD      s0, $01
                    LOAD      s1, $00
                    LOAD      s8, $10
                    LOAD      s9, $10

                    OUT       s0, signal1              ; signal1 is high
loop1:        OUT       s0, signal2              ; signal2 is high
                    CALL      delay                        ; delay for 773 instructions i.e., 1546 cycles
                    OUT       s1, signal2              ; signal2 is low
                    CALL      delay                        ; delay for773 instructions i.e., 1546 cycles
                    SUB       s8, $01                     ; decrement counter
                    JUMP      NZ, loop1                ; zero flag is set if contents of sF register becomes zero
                    OUT       s1, signal1               ; signal1 is low
loop2:         OUT       s0, signal2               ; signal2 is high
                    CALL      delay2                      ; delay for 736 instructions i.e., 1472 cycles

                    IN        s0, sd0_0                   ; Input Serial Data
                  ;  IN        s1, sd0_1
                    IN        s2, sd0_2
                    IN        s3, sd0_3
                    IN        s4, sd0_4
                    IN        s5, sd0_5
                    IN        s6, sd0_6
                    IN        s7, sd0_7
                    IN        s8, sd0_8
                   ; IN        s9, sd0_9
                    IN        sA, sd0_10
                    IN        sB, sd0_11
                    IN        sC, sd0_12
                    IN        sD, sd0_13
                    IN        sE, sd0_14
                    IN        sF, sd0_15
                    
                    SLA       s0                    ; Shift data into result registers
                  ;  SLA       s1
                    SLA       s2
                    SLA       s3
                    SLA       s4
                    SLA       s5
                    SLA       s6
                    SLA       s7
                    SLA       s8
                  ;  SLA       s9
                    SLA       sA
                    SLA       sB
                    SLA       sC
                    SLA       sD
                    SLA       sE
                    SLA       sF
                    
              
                    OUT       s1, signal2         ; signal2 is low
                    CALL      delay3                ; delay for 773 instructions i.e., 1546 cycles
                    SUB       s9, $01               ; decrement counter
                    JUMP      NZ, loop2           ; zero flag is set if contents of sF register becomes zero

                    JUMP      start


; delay routines

delay:          LOAD      s2, $16
big:              LOAD      s3, $10
small:         SUB       s3, $01
                    JUMP      NZ, small
                    SUB       s2, $01
                    JUMP      NZ, big
                    RET       

delay2:        LOAD      s2, $15
big2:            LOAD      s3, $10
small2:       SUB       s3, $01
                    JUMP      NZ, small2
                    SUB       s2, $01
                    JUMP      NZ, big2
                    RET

delay3:        LOAD      s2, $16
big3:            LOAD      s3, $10
small3:       SUB       s3, $01
                    JUMP      NZ, small3
                    SUB       s2, $01
                    JUMP      NZ, big3
                    RET

Since Picoblaze has only 16 registers, how can I use (mentioned in bold) instructions in loop2 which are commented ?

If I use those instructions, the next instructions(mentioned below) take the input values of serial data, which modifies my logic on the whole misleading the logic programmed.

OUT       s1, signal2         ; signal2 is low

SUB       s9, $01               ; decrement counter

How can I modify the above code such that 16-bit serial data is given as input ?

Please help me.

[eteam00]

I have one problem now.

That's an understatement.  You are completely impervious to my advice, and I've run out of reasonable ideas.

- Bob Elkind

[bassman59]

---

eteam00 wrote:

I have one problem now.

That's an understatement.  You are completely impervious to my advice, and I've run out of reasonable ideas.

- Bob Elkind

---

Bob, here is a reasonable idea: he refuses the life preserver. Let him sink.

[maverick_fc]

Hi all,

I have 16-bit input as mapped to ports below.

I'm shifting left to get MSB values first.

This operation is done during signal2 low and signal1 high.

; Port Mapping
serial_data_byte_one DSIN     $00

serial_data_LSB0    EQU       1
serial_data_LSB1    EQU       2
serial_data_LSB2    EQU       4
serial_data_LSB3    EQU       8
serial_data_LSB4    EQU       16
serial_data_LSB5    EQU       32
serial_data_LSB6    EQU       64
serial_data_LSB7    EQU       $80

serial_data_byte_two DSIN     $01

serial_data_MSB0    EQU       1
serial_data_MSB1    EQU       2
serial_data_MSB2    EQU       4
serial_data_MSB3    EQU       8
serial_data_MSB4    EQU       16
serial_data_MSB5    EQU       32
serial_data_MSB6    EQU       64
serial_data_MSB7    EQU       $80


signal1             DSOUT     $00                 ; 1.0008 KHz
signal2             DSOUT     $01                 ; 32.341 KHz
;
start:           LOAD      s0, $01
                    LOAD      s1, $00
                    LOAD      s8, $10
                    LOAD      s9, $10

                    OUT       s0, signal1               ; signal1 is high

loop1:         OUT       s0, signal2               ; signal2 is high
                    CALL      delay                       
                    OUT       s1, signal2               ; signal2 is low
                    CALL      delay_new             

                    IN        sA, serial_data_byte_one
                    IN        sB, serial_data_byte_two

                    SLA       sA
                    SLA       sB

                    SUB       s8, $01             ; decrement counter
                    JUMP      NZ, loop1           ; zero flag is set if contents of sF register becomes zero

                    OUT       s1, signal1         ; signal1 is low

loop2:         OUT       s0, signal2         ; signal2 is high
                    CALL      delay              
                    OUT       s1, signal2  

                    CALL      delay
                    SUB       s9, $01             ; decrement counter
                    JUMP      NZ, loop2           ; zero flag is set if contents of sF register becomes zero

                    JUMP      start


; delay routines

delay:          LOAD      s2, $16
big:              LOAD      s3, $10
small:         SUB       s3, $01
                    JUMP      NZ, small
                    SUB       s2, $01
                    JUMP      NZ, big
                    RET       

delay_new:            LOAD      s2, $15
big_new:                LOAD      s3, $10
small_new:           SUB       s3, $01
                                JUMP      NZ, small_new
                                SUB       s2, $01
                              JUMP      NZ, big_new
                              RET       

Please give feedback.

How do I map 16-bit input to a signal in the top-level module so that I can get parallel data ?