01-17-2011 12:15 PM
I am a bit of a novice with this technology so you will have to bear with me. As part of my University course, I am using the ISE web pack along with the Spartan 3E starter kit to create a simple sampling system, using the Picoblaze processor.
I have initially created a small test program using the Picoblaze uP which runs fine on the starter kit.
Next I wanted to implement the JTAG loader as I intend to write a much bigger ASM program and so reckoned it will save a lot of time. I followed the instructions in the user guide, replacing the ROM_form.vhd file with the Jtag_loader_ROM_form.vhd (renamed - chopped off the 'Jtag_loader' bit), and re-ran the assembler program. Assembler program worked fine and produced the new ROM file.
I removed the old rom file from the project and then added the new one. Symbol seemed ok, with the additional ports on the ROM block clearly there on the schematic.
Now the problem - For some reason, when I try to sythesise the project with the newly created ROM file, I get the error below:
- ERROR:HDLParsers:3312 - "C:/FPGA/HS_1/HSASM.VHD" Line 302. Undefined symbol 'BSCAN_VIRTEX2'.
Does anyone have any ideas what this could be? Any help would be greatly appreciated.
Many thanks (in advance) - Dave
Solved! Go to Solution.
01-17-2011 02:13 PM
I have done a screen dump of my project files below which highlights the problem:
I have just tried inserting a pre-scripted picoblaze rom file from one of the Spartan 3E reference designs on the Xilinx website but get the same problem.
Any help would be greatly appreciated.
01-18-2011 12:46 PM
Hi all, managed to get this to work, please see my solution below, hope this helps someone :smileyhappy:
I realised (took me a while :smileysad:) that the instance of boundary scan hardware defined in the module supplied with in the Jtag quick loader folder (supplied with Picoblaze) is not for the Spartan 3E device. I had to copy and paste the code from
-- BSCAN_SPARTAN3: Boundary Scan primitive for connecting internal logic to
-- JTAG interface. Spartan-3
-- Xilinx HDL Libraries Guide version 8.1i
BSCAN_SPARTAN3_inst : BSCAN_SPARTAN3
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK1 => DRCK1, -- Data register output for USER1 functions
DRCK2 => DRCK2, -- Data register output for USER2 functions
RESET => RESET, -- Reset output from TAP controller
SEL1 => SEL1, -- USER1 active output
SEL2 => SEL2, -- USER2 active output
SHIFT => SHIFT, -- SHIFT output from TAP controller
TDI => TDI, -- TDI output from TAP controller
UPDATE => UPDATE, -- UPDATE output from TAP controller
TDO1 => TDO1, -- Data input for USER1 function
TDO2 => TDO2 -- Data input for USER2 function
-- End of BSCAN_SPARTAN3_inst instantiation