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Regular Visitor
mellis
Posts: 36
Registered: ‎12-02-2010
0

Multiple Picoblaze and Chipscope issues

I have a Virtex6 design with multiple independent Picoblaze instances doing a variety of tasks for me.  I encountered packing errors (Pack:2811) and eventually found that I must set KeepHierarchy to "Soft" in order to work around this bug.  I have now added a Chipscope module and I am encountering the same packing errors.  If I remove the Chipscope I eliminate the error.

 

I found a couple of threads that discuss these issues but I do not see any resolution to the problem.  I have not yet tried placing registers between the PB and CS to see if the design will compile.  Are these issues being addressed by Xilinx?

 

http://forums.xilinx.com/t5/Synthesis/Keeping-Hierarchy-causes-packing-error-with-PicoBlaze-6/td-p/1...

http://forums.xilinx.com/t5/PicoBlaze/Picoblaze-Chipscope-Coexistence/m-p/122236

 

 

Regular Visitor
mellis
Posts: 36
Registered: ‎12-02-2010
0

Re: Multiple Picoblaze and Chipscope issues

Sorry, I should have stated that I'm using the ISE 13.1 toolset.
Expert Contributor
joelby
Posts: 1,056
Registered: ‎10-05-2010
0

Re: Multiple Picoblaze and Chipscope issues


 I found a couple of threads that discuss these issues but I do not see any resolution to the problem.  I have not yet tried placing registers between the PB and CS to see if the design will compile.  Are these issues being addressed by Xilinx? 


Add the registers - this will fix it.

 

It sounded like it was being investigated, but the workaround is perfectly adequate for now.

Regular Visitor
mellis
Posts: 36
Registered: ‎12-02-2010
0

Re: Multiple Picoblaze and Chipscope issues

The saga continues...

 

As I mentioned, I have multiple Picoblaze instances in my design.  Using the registers between Picoblaze and Chipscope allowed me to debug the first instance.  I have now shifted to the second Picoblaze and have encountered a new problem.  I now have Chipscope attached to my second Picoblaze using registers to isolate the two.  When I compile the design I get all the way to Bitgen and receive the following error messages:

 

ERROR:PhysDesignRules:2108 - Issue with pin connections and/or configuration on   block:<instFlashInterface/Mram_LchipTable>:<RAMB18E1_RAMB18E1>.  For TDP or   SDP mode, REGCLKARDRCLK should be tied off to 0 when DOA_REG is 0.

 

ERROR:PhysDesignRules:2105 - Issue with pin connections and/or configuration on   block:<instFlashInterface/Mram_LchipTable>:<RAMB18E1_RAMB18E1>.  For TDP   mode, REGCLKB should be tied off to 0 when DOB_REG is 0.

 

I have found that if I still get these errors when I disconnect the registers from the Picoblaze and connect them to ground.

 

genChipscope : if (ChipScope) generate

begin

    -- register picoblaze signals to isolate from chipscope

    -- this eliminates a PACK:2811 bug in the design tools

    process (SysClk)

    begin

        if rising_edge(SysClk) then                                 -- if rising edge of clock

            address_c        <= (others => '0');

            instruction_c    <= (others => '0');

            in_port_c        <= (others => '0');

            out_port_c       <= (others => '0');

            port_id_c        <= (others => '0');

            misc_c           <= (others => '0');

--            address_c        <= address;

--            instruction_c    <= instruction;

--            in_port_c        <= in_port;

--            out_port_c       <= out_port;

--            port_id_c        <= port_id;

--            misc_c           <= "00000" & k_write_strobe & write_strobe & read_strobe;

        end if;

    end process;

 

        -- instantiate chipscope ILA unit

    instila : ila_picoblaze port map (

        control                 => ila_control,

        clk                     => SysClk,

        trig0                   => address_c,

        trig1                   => instruction_c,

        trig2                   => in_port_c,

        trig3                   => out_port_c,

        trig4                   => port_id_c,

        trig5                   => misc_c

    );

end generate;

 

 

 

Regular Visitor
mellis
Posts: 36
Registered: ‎12-02-2010
0

Re: Multiple Picoblaze and Chipscope issues

Oops, the error message said nothing about Picoblaze.  I saw the reference to block ram and thought it referred to the Picoblaze block rams.  I had so much trouble getting PB and CS to play nice with each other and thought this was more of the same.

Regular Visitor
mellis
Posts: 36
Registered: ‎12-02-2010
0

Re: Multiple Picoblaze and Chipscope issues

For what it's worth, the workaround for this latest bug is to manually edit the XCO file for each ILA generated by coregen and change the line

 

"CSET disable_save_keep=false"

 

to

 

"CSET disable_save_keep=true"

 

Regenerate the ILA core and away you go...

Regular Contributor
gbredthauer
Posts: 91
Registered: ‎02-27-2008
0

Re: Multiple Picoblaze and Chipscope issues

Just as another data point - I was also getting Pack:2811 errors using a single Picoblaze and no Chipscope in an XC6VLX130.  I'm successfully using the newer V6 version of Picoblaze in a previous XC6VLX130 design, so I'm not sure what the difference was in this design.  I didn't have the time to dig, so I just reverted to the older Picoblaze implementation.  Not optimal, but time is valuable.

Regular Visitor
mellis
Posts: 36
Registered: ‎12-02-2010
0

Re: Multiple Picoblaze and Chipscope issues

Do you have multiple instances of Picoblaze in your design?  I saw the PACK:2811 errors with no Chipscope when I had multiple Picoblaze instances and KEEP HIERARCHY = YES in Synthesis proterties.  Setting this to SOFT worked around the problem.

Regular Visitor
mellis
Posts: 36
Registered: ‎12-02-2010
0

Re: Multiple Picoblaze and Chipscope issues

Sorry, I see the "single Picoblaze" in your message.