PicoBlaze FAQ – Multiple PicoBlaze Designs

chapman · ‎09-05-2007

It is quite common to have more than one PicoBlaze in a design and several users have reported having 8 or more even in a small Spartan device. In the many cases these processor instances operate independently just as you might expect different sections of a hardware design to have their own controlling state machines.

There are no special challenges to including multiple PicoBlaze processors in a design. In essence, every processor is completely independent and it is only down to you if you want them to interact and any connectivity is totally your decision.

Obviously you need to ensure all instantiation instances of the KCPSM3, their associated program memories and all their connecting signals are unique. Either create different signal names such as ‘proc1_write_strobe’ and ‘proc2_write_strobe’ or exploit hierarchy in your design which will hierarchically qualify all names to achieve the same unique names automatically. It makes sense to name each PicoBlaze program (PSM file) with a unique name as assembly results in the corresponding VHDL or Verilog description which you then include in your design project.

The following reference design for the Spartan-3E Starter Kit includes two PicoBlaze processors showing that this is all a straightforward design process.

http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm

Low Cost Design Authentication for Spartan-3E FPGAs
This design introduces a low cost design authentication technique which can be an effective deterrent to prevent malicious copying of designs. The unique ID of the Intel StrataFlash parallel NOR memory is the key feature used in this design. Please note that this design is for the more experienced user of Spartan-3E FPGAs.

The only specific issue encountered when creating a design with more than one PicoBlaze is that JTAG_loader can only to update one program BRAM at a time during program development. This is where the DATA2MEM flow is often more suitable as this enables any program to be modified during a given iteration. In fact you could modify all instances at the same time but changing too much at the same time is not normally consistent with standard debugging procedures where you attempt to eliminate one issue at a time. A description of how to used DATA2MEM is supplied with PicoBlaze.

Of course it is just as likely that multiple PicoBlaze processors will require some degree of communication. Since everything is inside an FPGA, you are totally free to define the interconnection that your require and it is impossible to make any specific recommendations about what is the best ‘network format’ as it should all relate to the requirements of your application.

Probably the best advice I can provide is that you should try and adopt communication schemes that still enable each processor to work as independently as possible. In that way each processor becomes less time critical and that leads to an easier task when writing your programs. As such, the use of small FIFO buffers when passing data from one processor to another is ideal. PicoBlaze is provides with some UART macros and these contain 16-byte FIFO buffers. The FIFO buffers are defined by the VHDL and Verilog files named ‘bbfifo_16x9’ and this 16-byte FIFO macro can be used independently. The reference design indicated above shows ‘bbfifo_16x9’ being used to link two PicoBlaze processors and enable an ASCII message to be passed from one to the other.

Another popular communication scheme is to use a dual port BRAM. Each processor has full read/write access of the memory and therefore information can be shared or exchanged. Experienced users may consider replacing the 64-byte scratch pad with a connection to a BRAM to provide 256-bytes of scratch pad memory (2048-bytes when using something else to define the upper 3 address bits). The second port of the same BRAM is then connected to a second PicoBlaze which has also had its scratch pad memory removed. The advantage of this scheme is that all I/O ports remain available. Note this is not something for a novice and you really must work through any issues yourself if you attempt this technique.

How about telling me how many processors you have in your design? I know a lot of MicroBlaze and PPC users also exploit PicoBlaze, but how many times?

Regards,

Ken Chapman

Ken Chapman
Principal Engineer, Xilinx UK

aortega · ‎10-24-2007

Hi Mr. Chapman! Thanks you for the design of KCPSM3. I think that is very clever!
I managed to fit 128 Picoblaze (With corresponding 1 Kb Instructions and 256 bytes of external memory) On a XUPV2P board that i happen to have. I am planning to do RC4 Cracking using them, In short I will be publishing the design and the source code (verilog and assembler) on my personal site.
I have some timings problems and the design won't run at the max speed of 200 MHZ, currently it only reaches 70 Mhz or so, but I am very new on FPGA design. In the future, i will post ask some questions in this forum with the hope that someone can help me to improve my design.

Regards,

Alfredo Ortega

naylor · ‎10-30-2007

I am working on a VLF radio design for through rock communications. The fast signal processing to perform single-sideband detection is done in logic (using System Generator). After filtering/demodulation/decimation, the data stream at audio rates can be handled by a processor such as the picoblaze for doing final agc/volume control etc. (plus cordic calculations to generate IQ voice components for emission). The device also has a user interface part that is nicely handled in another picoblaze processor. This generic structure I believe to be very powerful for many applications (DSP in logic/Picoblaze DSP treatment of filterred rate data/Picoblaze user interface). The user interface has a link to a serial port using Ken's UART and a small LCD using Ken's pico-code. The serial port is planned to be coupled via remote clients via bluetooth (headsets/mobile phones etc...) using the serial profile. In order to do program development and to allow future upgrades it is useful to download programs via the serial port (or across the bluetooth/serial link) as the jtag port will not be accesible. It is also necessary to re-program the two picoblazes. Here is a link to a bit of code that is preloaded on the user picoblaze that allows the user picoblaze to be re-loaded with a program starting at $20 (so only locations 0-$1F are lost for this bootloader) and to load the full program of the DSP picoblaze (which must be loaded first):

http://www.systemnicola.org/bootloadprog

regards

Graham

nibbs

quangngoc · ‎01-09-2009

Hello

Now I have started study about soft CPU, as PicoBlaze and MicroBlaze. Can you help me which tools or software that I need to complete a project about embedded CPU.

bassman59 · ‎02-25-2008

quangngoc wrote:
Hello
Now I have started study about soft CPU, as PicoBlaze and MicroBlaze. Can you help me which tools or software that I need to complete a project about embedded CPU.

To use MicroBlaze you must use the Xilinx EDK.

To use PicoBlaze, just download the assembler and the core.

There is a ton of available documentation about how to use both.

-a

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Yes, I do this for a living.

quangngoc · ‎01-09-2009

Only need ISE and EDK?

Do you think that I don't need buy a MicroBlaze core? I'm a starter. Can you tell me more specific?Thanks for your help

quangngoc · ‎01-09-2009

Hello!

Now I want build a embedded 8 bits CPU and other component as adder,FFT,... then connection them to build a system. Can I do it and how can I do it? Which tool or software I need? Thanks for your help.

bassman59 · ‎02-25-2008

quangngoc wrote:
Only need ISE and EDK?
Do you think that I don't need buy a MicroBlaze core? I'm a starter. Can you tell me more specific?Thanks for your help

When you pay for the EDK, you get a royalty-free license to use the MicroBlaze in your designs. I believe that this is all made clear in the relevant documentation.

-a

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Yes, I do this for a living.