01-26-2012 07:34 PM
I have two Spartan3E Starter Kit boards and downloaded PicoBlaze reference design files for PicoBlaze Frequency Counter and PicoBlaze Frequency Generator. On one of the board I run install_frequency_generator.bat to make it a signal generator. On the second board I run install_frequency_counter.bat to make it as a frequency counter. On the first board the frequency is set at 0.1 MHz. The output signal of the first board is connected to the input of second board by connecting both SMA connectors with a cable. The expected frequency reading on the second board is 100 kHz, but the actual reading is 199.993 kHz. It's twice of the expected value. What is the problem?
01-27-2012 08:14 AM
Likely the signal integrity of the connection has reflections, overshoot, and undershoot, which leads to two clocks senses per cycle.
Look at the signal with an oscilloscope. Try terminating the signal with split 100 ohm resistors to Vcc and ground.
Xilinx San Jose
01-27-2012 02:48 PM
Another thing you can try quickly might be to reduce the drive strength on the clock source.
LVCMOS 4 mA might have enough effective source resistance to prevent ringing, or at least
reduce it to the point where the reflection doesn't cross the logic threshold.
01-28-2012 08:19 PM - edited 01-28-2012 08:55 PM
Try terminating the signal with split 100 ohm resistors to Vcc and ground.
Or a single AC-coupled 100 ohm resistor to ground.
load pin |<-+------------------------------<signal from source
added: +--/\/\------||----| GND
100 ohm 0.01uF
-- Bob Elkind
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03-19-2013 04:07 AM
hi,i am trying to use the picoblaze implemented frequency counter using KCPSM3...............its the same program given on xilinx frequence counter which is for Spartan 3E XC500E . but i am having a spartan 3 kit and i am trying to program it on spartan 3 ,i am getting some errors which i am unable to solve ...can some one help me with the errors............
the errors are:-
Pack:679 - Unable to obey design constraints (LOC=SLICE_X8Y29) which
require the combination of the following symbols into a single SLICEM
MUXCY symbol "processor/sel_shadow_muxcy" (Output Signal =
MUXCY symbol "processor/zero_cymux" (Output Signal = processor/zero_carry)
The carry muxes are not connected in the required manner. Please correct the
design constraints accordingly.
03-20-2013 11:28 AM
I apologise to all readers for adding the threads other than the existing issue. I suggest you ignore my previous message.