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Questions on PicoBlaze PWM Reference Design?
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12-27-2007 12:21 AM
Re: Questions on PicoBlaze PWM Reference Design?
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12-30-2007 05:43 AM
I think most of this is covered pretty well on pages 12-14
of the reference design document especially when read in conjunction with the
design source files and their inline comments. As to the UART baud rate, this
is described in the ‘UART_manual.pdf’ provided with PicoBlaze and again in the comments
contained in the VHDL source code.
The design uses the 50MHz oscillator on the starter kit board;
so that is a 20ns clock period.
For a PRF of 1KHz and a duty cycle resolution of 8 bits then
PicoBlaze is required to drive the PWM outputs with the required values every 1/(1000x256)
= 3.92us. So therefore PicoBlaze is
interrupted every 3.91us to perform the PWM updates. To generate the interrupt
a counter is used to count the required number of clock cycles which is 3.92us/20ns
= 196. Therefore a counter with states 0 to 195 and a decode of 195.
Each interrupt requires PicoBlaze to determine the drive
value for each PWM output. This takes a number of instructions to achieve and
because each instruction requires 2 clock cycles to execute this takes time. We
know there is an interrupt every 196 clock cycles and therefore PicoBlaze can
only execute 97 instructions between interrupts. Currently the interrupt service
routine to drive all 12 PWM outputs requires approximately half of the 97 instructions.
For a baud rate of 9600 the UART macros require a reference 16 times faster at 153600Hz. This is generated using another counter operating at 50MHz so that requires 50MHz/153600 = 326 states and hence a count range of 0 to 325 with a decode of 325.
Regards,
Ken
Principal Engineer, Xilinx UK
Re: Questions on PicoBlaze PWM Reference Design?
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01-03-2008 06:48 PM
Re: Questions on PicoBlaze PWM Reference Design?
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03-12-2011 07:16 AM - edited 03-12-2011 07:44 AM
hi,
i read pwm.pdf and i saw that the pulse repeated every 1ms(1kHz),but i want continuous signal with PRF=50Hz(20ms) and the pulse changes from 0.5ms to 2.5ms ,i meen that i want control increase or decrease the range( 0.5ms to 2.5ms ) and this pulse overall period is repeated every 20ms.can this done in picoblaze with PWM ? did this reach the software limits?what i change in program to perform this signal? how much the value of interrupt counter?
note:this signal to control 5 dc servo motor, so need 5 channels only .
thanks...
Re: Questions on PicoBlaze PWM Reference Design?
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03-14-2011 06:50 AM
Let’s write down the variables that apply to your case and work it out….
System clock frequency – You haven’t told me that one but let me assume 50MHz for now. PicoBlaze executes an instruction every 2 clock cycles to that means it can execute 25 million instructions per second. That’s one instruction every 40ns.
Number of channels - You tell us 5 so that is clearly defined.
Pulse Repetition Frequency (PRF) or Pulse Repetition Interval (PRI) – Here you need 50Hz or 20ms.
Duty cycle resolution – This is what you have not stated yet. You have told us that you need to vary the duty cycle between 0.5ms and 2.5ms which is only 10% of the complete 20ms range but you do not saw with what resolution you need to make that change. For now I will assume that a resolution of 0.1ms is enough resolution but that really is something you need to work out because it makes all the difference.
So the real key points are the duty cycle resolution and the clock rate. If 0.1ms resolution was adequate then using the PWM scheme implemented in my reference design that would mean that PicoBlaze would be interrupted at 0.1ms intervals using an external counter circuit. 0.1ms at 50MHz equates to 5,000 clock cycles. This also tells us that PicoBlaze could execute 2,500 instructions between each interrupt which really is a lot! In other words, PicoBlaze has lots of capability to handle the 5 channels that you need and you are nowhere near the software limit.
However, if you needed a resolution of 1us then that would mean an interrupt every 50 clock cycles and PicoBlaze could only execute 25 instructions each time. My guess is that would be right on the limit for 5 channels and PicoBlaze would never have time to do anything else.
Principal Engineer, Xilinx UK
Re: Questions on PicoBlaze PWM Reference Design?
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03-17-2011 01:29 PM
hi Mr. Chapman
thanks for your answer,it is very clear.
My system clock frequency is 50MHz and the resolution i need to make that change is vary from 10us to 100us to i can control the speed of motor rotation,this value must be change by software to control the speed,so how i can change the interrupt counter value by software? can i put the lowest value(10us) in counter? i need your suggestion on if i need to design external hardware system(VHDL) and i control it using Picoblaze or i need to use multiple picoblaze for control the speed and position(pulse width value) and how many channels can each picoblaze perform if i have 13 motor (channels).
thanks very much..
Re: Questions on PicoBlaze PWM Reference Design?
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03-18-2011 10:27 AM
All PicoBlaze based designs involve hardware (HDL) design because that is what an FPGA is all about and where PicoBlaze lives. What you implement in pure hardware and what you implement in soft PSM code is both personal choice and driven by the performance demands of a function. I recommend you read the following FAQ....
http://forums.xilinx.com/t5/PicoBlaze/PicoBlaze-FA
Then I think the thing you most need to do is write down a proper specification so that you can make implementation decisions. As with many projects there is always some initial uncertainly but based on what you have said so far you have not really decided if you need 5 or 13 PWM channels or know what the PWM resolution needs to be so you really need to narrow down on those choices. Take some time now to study the material already available to you and actually try some physical experiments with an FPGA and at least one motor. That should help you refine your specifications and you should also see practically what PicoBlaze and pure hardware each do well such that your final design implementation follows on naturally.
Principal Engineer, Xilinx UK











